diff --git a/src/amd/vulkan/meta/radv_meta_resolve.c b/src/amd/vulkan/meta/radv_meta_resolve.c
index 5f9d45629f9..b485d3c234e 100644
--- a/src/amd/vulkan/meta/radv_meta_resolve.c
+++ b/src/amd/vulkan/meta/radv_meta_resolve.c
@@ -537,6 +537,17 @@ radv_cmd_buffer_resolve_rendering(struct radv_cmd_buffer *cmd_buffer)
 
    radv_describe_begin_render_pass_resolve(cmd_buffer);
 
+   /* Resolves happen before the end-of-subpass barriers get executed, so we have to make the
+    * attachment shader-readable.
+    */
+   struct radv_resolve_barrier barrier;
+   barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
+   barrier.dst_stage_mask = VK_PIPELINE_STAGE_2_RESOLVE_BIT;
+   barrier.src_access_mask = (has_color_resolve ? VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT : 0) |
+                             (has_ds_resolve ? VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT : 0);
+   barrier.dst_access_mask = VK_ACCESS_2_SHADER_READ_BIT;
+   radv_emit_resolve_barrier(cmd_buffer, &barrier);
+
    if (render->ds_att.resolve_iview != NULL) {
       struct radv_image_view *src_iview = render->ds_att.iview;
       struct radv_image_view *dst_iview = render->ds_att.resolve_iview;
@@ -590,20 +601,10 @@ radv_cmd_buffer_resolve_rendering(struct radv_cmd_buffer *cmd_buffer)
    if (has_color_resolve) {
       uint32_t layer_count = render->layer_count;
       VkRect2D resolve_area = render->area;
-      struct radv_resolve_barrier barrier;
 
       if (render->view_mask)
          layer_count = util_last_bit(render->view_mask);
 
-      /* Resolves happen before the end-of-subpass barriers get executed, so we have to make the
-       * attachment shader-readable.
-       */
-      barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
-      barrier.dst_stage_mask = VK_PIPELINE_STAGE_2_RESOLVE_BIT;
-      barrier.src_access_mask = VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT;
-      barrier.dst_access_mask = VK_ACCESS_2_SHADER_READ_BIT;
-      radv_emit_resolve_barrier(cmd_buffer, &barrier);
-
       for (uint32_t i = 0; i < render->color_att_count; ++i) {
          if (render->color_att[i].resolve_iview == NULL)
             continue;
diff --git a/src/amd/vulkan/meta/radv_meta_resolve_cs.c b/src/amd/vulkan/meta/radv_meta_resolve_cs.c
index 525530379ad..f56990a5a39 100644
--- a/src/amd/vulkan/meta/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/meta/radv_meta_resolve_cs.c
@@ -506,15 +506,6 @@ radv_depth_stencil_resolve_rendering_cs(struct radv_cmd_buffer *cmd_buffer, VkIm
    if (render->view_mask)
       layer_count = util_last_bit(render->view_mask);
 
-   /* Resolves happen before the end-of-subpass barriers get executed, so
-    * we have to make the attachment shader-readable.
-    */
-   cmd_buffer->state.flush_bits |=
-      radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
-                            VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, 0, NULL, NULL) |
-      radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT, VK_ACCESS_2_SHADER_READ_BIT, 0, NULL,
-                            NULL);
-
    struct radv_image_view *src_iview = render->ds_att.iview;
    VkImageLayout src_image_layout =
       aspects & VK_IMAGE_ASPECT_DEPTH_BIT ? render->ds_att.layout : render->ds_att.stencil_layout;
diff --git a/src/amd/vulkan/meta/radv_meta_resolve_fs.c b/src/amd/vulkan/meta/radv_meta_resolve_fs.c
index 4acfc2395b9..4ab4b9d5f1d 100644
--- a/src/amd/vulkan/meta/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/meta/radv_meta_resolve_fs.c
@@ -718,14 +718,6 @@ radv_depth_stencil_resolve_rendering_fs(struct radv_cmd_buffer *cmd_buffer, VkIm
                                         VkResolveModeFlagBits resolve_mode)
 {
    const struct radv_rendering_state *render = &cmd_buffer->state.render;
-   struct radv_resolve_barrier barrier;
-
-   /* Resolves happen before rendering ends, so we have to make the attachment shader-readable */
-   barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
-   barrier.dst_stage_mask = VK_PIPELINE_STAGE_2_RESOLVE_BIT;
-   barrier.src_access_mask = VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
-   barrier.dst_access_mask = VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT;
-   radv_emit_resolve_barrier(cmd_buffer, &barrier);
 
    struct radv_image_view *src_iview = render->ds_att.iview;
    VkImageLayout src_image_layout =