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nak: Implement fmulz and ffmaz
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10261 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26569>
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parent
ce8d966085
commit
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2 changed files with 8 additions and 4 deletions
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@ -123,6 +123,10 @@ fn nir_options(dev: &nv_device_info) -> nir_shader_compiler_options {
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op.has_sudot_4x8 = dev.sm >= 70;
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op.has_sudot_4x8 = dev.sm >= 70;
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op.max_unroll_iterations = 32;
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op.max_unroll_iterations = 32;
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// We set .ftz on f32 by default so we can support fmulz whenever the client
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// doesn't explicitly request denorms.
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op.has_fmulz_no_denorms = true;
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op
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op
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}
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}
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@ -703,7 +703,7 @@ impl<'a> ShaderFromNir<'a> {
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dst
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dst
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}
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}
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nir_op_fexp2 => b.mufu(MuFuOp::Exp2, srcs[0]),
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nir_op_fexp2 => b.mufu(MuFuOp::Exp2, srcs[0]),
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nir_op_ffma => {
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nir_op_ffma | nir_op_ffmaz => {
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let ftype = FloatType::from_bits(alu.def.bit_size().into());
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let ftype = FloatType::from_bits(alu.def.bit_size().into());
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assert!(alu.def.bit_size() == 32);
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assert!(alu.def.bit_size() == 32);
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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@ -713,7 +713,7 @@ impl<'a> ShaderFromNir<'a> {
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saturate: self.try_saturate_alu_dst(&alu.def),
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saturate: self.try_saturate_alu_dst(&alu.def),
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rnd_mode: self.float_ctl[ftype].rnd_mode,
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rnd_mode: self.float_ctl[ftype].rnd_mode,
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ftz: self.float_ctl[ftype].ftz,
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ftz: self.float_ctl[ftype].ftz,
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dnz: false,
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dnz: alu.op == nir_op_ffmaz,
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});
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});
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dst
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dst
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}
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}
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@ -732,7 +732,7 @@ impl<'a> ShaderFromNir<'a> {
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});
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});
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dst
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dst
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}
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}
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nir_op_fmul => {
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nir_op_fmul | nir_op_fmulz => {
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let ftype = FloatType::from_bits(alu.def.bit_size().into());
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let ftype = FloatType::from_bits(alu.def.bit_size().into());
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assert!(alu.def.bit_size() == 32);
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assert!(alu.def.bit_size() == 32);
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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@ -742,7 +742,7 @@ impl<'a> ShaderFromNir<'a> {
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saturate: self.try_saturate_alu_dst(&alu.def),
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saturate: self.try_saturate_alu_dst(&alu.def),
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rnd_mode: self.float_ctl[ftype].rnd_mode,
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rnd_mode: self.float_ctl[ftype].rnd_mode,
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ftz: self.float_ctl[ftype].ftz,
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ftz: self.float_ctl[ftype].ftz,
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dnz: false,
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dnz: alu.op == nir_op_fmulz,
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});
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});
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dst
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dst
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}
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}
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