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r300/compiler: lower CEIL
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parent
e53a1576dd
commit
394803b2cd
4 changed files with 34 additions and 2 deletions
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@ -115,7 +115,7 @@ static unsigned translate_opcode(unsigned opcode)
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/* case TGSI_OPCODE_ENDREP: return RC_OPCODE_ENDREP; */
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/* case TGSI_OPCODE_PUSHA: return RC_OPCODE_PUSHA; */
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/* case TGSI_OPCODE_POPA: return RC_OPCODE_POPA; */
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/* case TGSI_OPCODE_CEIL: return RC_OPCODE_CEIL; */
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case TGSI_OPCODE_CEIL: return RC_OPCODE_CEIL;
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/* case TGSI_OPCODE_I2F: return RC_OPCODE_I2F; */
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/* case TGSI_OPCODE_NOT: return RC_OPCODE_NOT; */
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/* case TGSI_OPCODE_TRUNC: return RC_OPCODE_TRUNC; */
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@ -59,6 +59,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
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.NumSrcRegs = 1,
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.HasDstReg = 1
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},
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{
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.Opcode = RC_OPCODE_CEIL,
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.Name = "CEIL",
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.NumSrcRegs = 1,
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.HasDstReg = 1,
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.IsComponentwise = 1
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},
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{
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.Opcode = RC_OPCODE_CMP,
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.Name = "CMP",
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@ -47,6 +47,9 @@ typedef enum {
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* dst.x = floor(src.x), where dst must be an address register */
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RC_OPCODE_ARL,
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/** vec4 instruction: dst.c = ceil(src0.c) */
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RC_OPCODE_CEIL,
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/** vec4 instruction: dst.c = src0.c < 0.0 ? src1.c : src2.c */
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RC_OPCODE_CMP,
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@ -175,6 +175,26 @@ static void transform_ABS(struct radeon_compiler* c,
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rc_remove_instruction(inst);
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}
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static void transform_CEIL(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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/* Assuming:
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* ceil(x) = -floor(-x)
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*
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* After inlining floor:
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* ceil(x) = -(-x-frac(-x))
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*
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* After simplification:
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* ceil(x) = x+frac(-x)
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*/
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int tempreg = rc_find_free_temporary(c);
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emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstreg(RC_FILE_TEMPORARY, tempreg), negate(inst->U.I.SrcReg[0]));
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emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
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inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, tempreg));
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rc_remove_instruction(inst);
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}
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static void transform_DP3(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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@ -458,7 +478,7 @@ static void transform_XPD(struct radeon_compiler* c,
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* no userData necessary.
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*
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* Eliminates the following ALU instructions:
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* ABS, DPH, DST, FLR, LIT, LRP, POW, SEQ, SFL, SGE, SGT, SLE, SLT, SNE, SUB, SWZ, XPD
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* ABS, CEIL, DPH, DST, FLR, LIT, LRP, POW, SEQ, SFL, SGE, SGT, SLE, SLT, SNE, SUB, SWZ, XPD
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* using:
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* MOV, ADD, MUL, MAD, FRC, DP3, LG2, EX2, CMP
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*
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@ -474,6 +494,7 @@ int radeonTransformALU(
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{
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switch(inst->U.I.Opcode) {
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case RC_OPCODE_ABS: transform_ABS(c, inst); return 1;
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case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
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case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
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case RC_OPCODE_DST: transform_DST(c, inst); return 1;
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case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
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@ -546,6 +567,7 @@ int r300_transform_vertex_alu(
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{
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switch(inst->U.I.Opcode) {
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case RC_OPCODE_ABS: transform_r300_vertex_ABS(c, inst); return 1;
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case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
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case RC_OPCODE_CMP: transform_r300_vertex_CMP(c, inst); return 1;
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case RC_OPCODE_DP3: transform_DP3(c, inst); return 1;
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case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
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