gv100/ir: set ftz bit on floating point operations

Fixes Unigine Heavens ambient occlusion

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5881>
This commit is contained in:
Karol Herbst 2020-07-13 16:24:20 +02:00 committed by Marge Bot
parent f95637f01a
commit 38e3cbb639
2 changed files with 8 additions and 2 deletions

View file

@ -35,7 +35,7 @@ GV100LegalizeSSA::handleCMP(Instruction *i)
Value *pred = bld.getSSA(1, FILE_PREDICATE);
bld.mkCmp(OP_SET, reverseCondCode(i->asCmp()->setCond), TYPE_U8, pred,
i->sType, bld.mkImm(0), i->getSrc(2));
i->sType, bld.mkImm(0), i->getSrc(2))->ftz = i->ftz;
bld.mkOp3(OP_SELP, TYPE_U32, i->getDef(0), i->getSrc(0), i->getSrc(1), pred);
return true;
}
@ -189,6 +189,7 @@ GV100LegalizeSSA::handleSET(Instruction *i)
xsetp->src(0).mod = i->src(0).mod;
xsetp->src(1).mod = i->src(1).mod;
xsetp->setSrc(2, src2);
xsetp->ftz = i->ftz;
i = bld.mkOp3(OP_SELP, TYPE_U32, i->getDef(0), bld.mkImm(0), met, pred);
i->src(2).mod = Modifier(NV50_IR_MOD_NOT);
@ -235,6 +236,7 @@ GV100LegalizeSSA::handleSUB(Instruction *i)
bld.mkOp2(OP_ADD, i->dType, i->getDef(0), i->getSrc(0), i->getSrc(1));
xadd->src(0).mod = i->src(0).mod;
xadd->src(1).mod = i->src(1).mod ^ Modifier(NV50_IR_MOD_NEG);
xadd->ftz = i->ftz;
return true;
}
@ -244,6 +246,9 @@ GV100LegalizeSSA::visit(Instruction *i)
bool lowered = false;
bld.setPosition(i, false);
if (i->sType == TYPE_F32 && i->dType != TYPE_F16 &&
prog->getType() != Program::TYPE_COMPUTE)
handleFTZ(i);
switch (i->op) {
case OP_AND:

View file

@ -64,13 +64,14 @@ private:
void handleDIV(Instruction *); // integer division, modulus
void handleRCPRSQLib(Instruction *, Value *[]);
void handleRCPRSQ(Instruction *); // double precision float recip/rsqrt
void handleFTZ(Instruction *);
void handleSET(CmpInstruction *);
void handleTEXLOD(TexInstruction *);
void handleShift(Instruction *);
void handleBREV(Instruction *);
protected:
void handleFTZ(Instruction *);
BuildUtil bld;
};