i965/device_info: Add a supports_simd16_3src flag

This also involves moving revision checking to screen creation time and
passing that into brw_get_device_info so that we can get the right
device_info for early versions of SKL.  Since the only place we used
revision was to check for SIMD16 3-src instruction support, it's safe to
remove the revision field from brw_context.

Reviewed-by: Matt Turner <mattst88@gmail.com>

src/mesa/drivers/dri/i965/brw_context.c

@@ -669,29 +669,6 @@ brw_process_driconf_options(struct brw_context *brw)
       driQueryOptionb(options, "allow_glsl_extension_directive_midshader");
 }
 
-/* drop when libdrm 2.4.61 is released */
-#ifndef I915_PARAM_REVISION
-#define I915_PARAM_REVISION 32
-#endif
-
-static int
-brw_get_revision(int fd)
-{
-   struct drm_i915_getparam gp;
-   int revision;
-   int ret;
-
-   memset(&gp, 0, sizeof(gp));
-   gp.param = I915_PARAM_REVISION;
-   gp.value = &revision;
-
-   ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
-   if (ret)
-      revision = -1;
-
-   return revision;
-}
-
 GLboolean
 brwCreateContext(gl_api api,
 	         const struct gl_config *mesaVis,
@@ -750,7 +727,6 @@ brwCreateContext(gl_api api,
    brw->has_negative_rhw_bug = devinfo->has_negative_rhw_bug;
    brw->needs_unlit_centroid_workaround =
       devinfo->needs_unlit_centroid_workaround;
-   brw->revision = brw_get_revision(sPriv->fd);
 
    brw->must_use_separate_stencil = screen->hw_must_use_separate_stencil;
    brw->has_swizzling = screen->hw_has_swizzling;

src/mesa/drivers/dri/i965/brw_context.h

@@ -1083,10 +1083,6 @@ struct brw_context
 
    int gen;
    int gt;
-   /* GT revision. This will be -1 if the revision couldn't be determined (eg,
-    * if the kernel doesn't support the query).
-    */
-   int revision;
 
    bool is_g4x;
    bool is_baytrail;

src/mesa/drivers/dri/i965/brw_device_info.c

@@ -166,7 +166,8 @@ static const struct brw_device_info brw_device_info_byt = {
 
 #define HSW_FEATURES             \
    GEN7_FEATURES,                \
-   .is_haswell = true
+   .is_haswell = true,           \
+   .supports_simd16_3src = true
 
 static const struct brw_device_info brw_device_info_hsw_gt1 = {
    HSW_FEATURES, .gt = 1,
@@ -225,6 +226,7 @@ static const struct brw_device_info brw_device_info_hsw_gt3 = {
    .must_use_separate_stencil = true,               \
    .has_llc = true,                                 \
    .has_pln = true,                                 \
+   .supports_simd16_3src = true,                    \
    .max_vs_threads = 504,                           \
    .max_hs_threads = 504,                           \
    .max_ds_threads = 504,                           \
@@ -305,27 +307,42 @@ static const struct brw_device_info brw_device_info_chv = {
       .max_gs_entries = 640,                        \
    }
 
+static const struct brw_device_info brw_device_info_skl_early = {
+   GEN9_FEATURES, .gt = 1,
+   .supports_simd16_3src = false,
+};
+
 static const struct brw_device_info brw_device_info_skl_gt1 = {
-   GEN9_FEATURES, .gt = 1
+   GEN9_FEATURES, .gt = 1,
+   .supports_simd16_3src = true,
 };
 
 static const struct brw_device_info brw_device_info_skl_gt2 = {
-   GEN9_FEATURES, .gt = 2
+   GEN9_FEATURES, .gt = 2,
+   .supports_simd16_3src = true,
 };
 
 static const struct brw_device_info brw_device_info_skl_gt3 = {
-   GEN9_FEATURES, .gt = 3
+   GEN9_FEATURES, .gt = 3,
+   .supports_simd16_3src = true,
 };
 
 const struct brw_device_info *
-brw_get_device_info(int devid)
+brw_get_device_info(int devid, int revision)
 {
+   const struct brw_device_info *devinfo;
    switch (devid) {
 #undef CHIPSET
-#define CHIPSET(id, family, name) case id: return &brw_device_info_##family;
+#define CHIPSET(id, family, name) \
+   case id: devinfo = &brw_device_info_##family; break;
 #include "pci_ids/i965_pci_ids.h"
    default:
       fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
       return NULL;
    }
+
+   if (devinfo->gen == 9 && (revision == 2 || revision == 3 || revision == -1))
+      return &brw_device_info_skl_early;
+
+   return devinfo;
 }

src/mesa/drivers/dri/i965/brw_device_info.h

@@ -44,6 +44,7 @@ struct brw_device_info
    bool has_pln;
    bool has_compr4;
    bool has_surface_tile_offset;
+   bool supports_simd16_3src;
 
    /**
     * Quirks:
@@ -82,4 +83,4 @@ struct brw_device_info
    /** @} */
 };
 
-const struct brw_device_info *brw_get_device_info(int devid);
+const struct brw_device_info *brw_get_device_info(int devid, int revision);

src/mesa/drivers/dri/i965/brw_fs_generator.cpp

@@ -1534,24 +1534,11 @@ fs_generator::enable_debug(const char *shader_name)
    this->shader_name = shader_name;
 }
 
-/**
- * Some hardware doesn't support SIMD16 instructions with 3 sources.
- */
-static bool
-brw_supports_simd16_3src(const struct brw_context *brw)
-{
-   /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
-    * on a few steppings of Skylake.
-    */
-   if (brw->gen == 9)
-      return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
-
-   return brw->is_haswell || brw->gen >= 8;
-}
-
 int
 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
 {
+   const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+
    /* align to 64 byte boundary. */
    while (p->next_insn_offset % 64)
       brw_NOP(p);
@@ -1647,7 +1634,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
       case BRW_OPCODE_MAD:
          assert(brw->gen >= 6);
 	 brw_set_default_access_mode(p, BRW_ALIGN_16);
-         if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
+         if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
             brw_set_default_exec_size(p, BRW_EXECUTE_8);
 	    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
             brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
@@ -1669,7 +1656,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
       case BRW_OPCODE_LRP:
          assert(brw->gen >= 6);
 	 brw_set_default_access_mode(p, BRW_ALIGN_16);
-         if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
+         if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
             brw_set_default_exec_size(p, BRW_EXECUTE_8);
 	    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
             brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
@@ -1808,7 +1795,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
       case BRW_OPCODE_BFE:
          assert(brw->gen >= 7);
          brw_set_default_access_mode(p, BRW_ALIGN_16);
-         if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
+         if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
             brw_set_default_exec_size(p, BRW_EXECUTE_8);
             brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
             brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
@@ -1851,7 +1838,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
           * do for the other three-source instructions.
           */
          if (dispatch_width == 16 &&
-             (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
+             (brw->is_haswell || !devinfo->supports_simd16_3src)) {
             brw_set_default_exec_size(p, BRW_EXECUTE_8);
             brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
             brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));

src/mesa/drivers/dri/i965/intel_screen.c

@@ -1304,6 +1304,29 @@ set_max_gl_versions(struct intel_screen *screen)
    }
 }
 
+/* drop when libdrm 2.4.61 is released */
+#ifndef I915_PARAM_REVISION
+#define I915_PARAM_REVISION 32
+#endif
+
+static int
+brw_get_revision(int fd)
+{
+   struct drm_i915_getparam gp;
+   int revision;
+   int ret;
+
+   memset(&gp, 0, sizeof(gp));
+   gp.param = I915_PARAM_REVISION;
+   gp.value = &revision;
+
+   ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
+   if (ret)
+      revision = -1;
+
+   return revision;
+}
+
 /**
  * This is the driver specific part of the createNewScreen entry point.
  * Called when using DRI2.
@@ -1340,7 +1363,8 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
        return false;
 
    intelScreen->deviceID = drm_intel_bufmgr_gem_get_devid(intelScreen->bufmgr);
-   intelScreen->devinfo = brw_get_device_info(intelScreen->deviceID);
+   intelScreen->devinfo = brw_get_device_info(intelScreen->deviceID,
+                                              brw_get_revision(psp->fd));
    if (!intelScreen->devinfo)
       return false;