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https://gitlab.freedesktop.org/mesa/mesa.git
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ir3: Make ir3_create_collect() take a block
There's no reason to make this any different from the other builders, since it just creates a collect instruction, and in the next commit we'll need to create a collect in the first block for prefetch textures. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
This commit is contained in:
Connor Abbott
Marge Bot
parent
8fb99b58df
commit
38a84723f1
5 changed files with 51 additions and 54 deletions
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@ -48,7 +48,7 @@ emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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offset = ir3_get_src(ctx, &intr->src[2])[0];
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/* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
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src0 = ir3_collect(ctx, byte_offset, create_immed(b, 0));
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src0 = ir3_collect(b, byte_offset, create_immed(b, 0));
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src1 = offset;
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ldgb = ir3_LDGB(b, ssbo, 0, src0, 0, src1, 0);
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@ -81,9 +81,9 @@ emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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/* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
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* nir already *= 4:
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*/
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src0 = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
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src0 = ir3_create_collect(b, ir3_get_src(ctx, &intr->src[0]), ncomp);
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src1 = offset;
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src2 = ir3_collect(ctx, byte_offset, create_immed(b, 0));
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src2 = ir3_collect(b, byte_offset, create_immed(b, 0));
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stgb = ir3_STGB(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
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stgb->cat6.iim_val = ncomp;
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@ -129,7 +129,7 @@ emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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struct ir3_instruction *data = ir3_get_src(ctx, &intr->src[2])[0];
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/* 64b byte offset */
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struct ir3_instruction *byte_offset =
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ir3_collect(ctx, ir3_get_src(ctx, &intr->src[1])[0], create_immed(b, 0));
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ir3_collect(b, ir3_get_src(ctx, &intr->src[1])[0], create_immed(b, 0));
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/* dword offset for everything but comp_swap */
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struct ir3_instruction *src3 = ir3_get_src(ctx, &intr->src[3])[0];
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@ -165,7 +165,7 @@ emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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break;
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case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
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/* for cmpxchg, src0 is [ui]vec2(data, compare): */
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data = ir3_collect(ctx, src3, data);
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data = ir3_collect(b, src3, data);
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struct ir3_instruction *dword_offset = ir3_get_src(ctx, &intr->src[4])[0];
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atomic = ir3_ATOMIC_CMPXCHG_G(b, ssbo, 0, data, 0, dword_offset, 0,
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byte_offset, 0);
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@ -225,7 +225,7 @@ get_image_offset(struct ir3_context *ctx, const nir_intrinsic_instr *instr,
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offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
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}
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return ir3_collect(ctx, offset, create_immed(b, 0));
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return ir3_collect(b, offset, create_immed(b, 0));
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}
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/* src[] = { deref, coord, sample_index }. const_index[] = {} */
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@ -242,7 +242,7 @@ emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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ir3_get_num_components_for_image_format(nir_intrinsic_format(intr));
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struct ir3_instruction *ldib = ir3_LDIB(
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b, ibo, 0, offset, 0, ir3_create_collect(ctx, coords, ncoords), 0);
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b, ibo, 0, offset, 0, ir3_create_collect(b, coords, ncoords), 0);
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ldib->dsts[0]->wrmask = MASK(intr->num_components);
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ldib->cat6.iim_val = ncomp;
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ldib->cat6.d = ncoords;
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@ -279,8 +279,8 @@ emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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* one over the other in various cases.
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*/
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stib = ir3_STIB(b, ibo, 0, ir3_create_collect(ctx, value, ncomp), 0,
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ir3_create_collect(ctx, coords, ncoords), 0, offset, 0);
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stib = ir3_STIB(b, ibo, 0, ir3_create_collect(b, value, ncomp), 0,
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ir3_create_collect(b, coords, ncoords), 0, offset, 0);
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stib->cat6.iim_val = ncomp;
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stib->cat6.d = ncoords;
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stib->cat6.type = ir3_get_type_for_image_intrinsic(intr);
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@ -306,7 +306,7 @@ emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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* src2 is 64b byte offset
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*/
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src0 = ir3_get_src(ctx, &intr->src[3])[0];
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src1 = ir3_create_collect(ctx, coords, ncoords);
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src1 = ir3_create_collect(b, coords, ncoords);
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src2 = get_image_offset(ctx, intr, coords, false);
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switch (intr->intrinsic) {
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@ -335,7 +335,7 @@ emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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break;
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case nir_intrinsic_image_atomic_comp_swap:
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/* for cmpxchg, src0 is [ui]vec2(data, compare): */
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src0 = ir3_collect(ctx, ir3_get_src(ctx, &intr->src[4])[0], src0);
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src0 = ir3_collect(b, ir3_get_src(ctx, &intr->src[4])[0], src0);
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atomic = ir3_ATOMIC_CMPXCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
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break;
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default:
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@ -74,7 +74,7 @@ emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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/* src0 is offset, src1 is value:
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*/
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val = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
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val = ir3_create_collect(b, ir3_get_src(ctx, &intr->src[0]), ncomp);
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offset = ir3_get_src(ctx, &intr->src[3])[0];
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stib = ir3_STIB(b, ir3_ssbo_to_ibo(ctx, intr->src[1]), 0, offset, 0, val, 0);
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@ -136,10 +136,10 @@ emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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if (intr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap_ir3) {
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src0 = ir3_get_src(ctx, &intr->src[4])[0];
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struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[3])[0];
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src1 = ir3_collect(ctx, dummy, compare, data);
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src1 = ir3_collect(b, dummy, compare, data);
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} else {
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src0 = ir3_get_src(ctx, &intr->src[3])[0];
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src1 = ir3_collect(ctx, dummy, data);
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src1 = ir3_collect(b, dummy, data);
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}
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switch (intr->intrinsic) {
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@ -207,7 +207,7 @@ emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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unsigned ncoords = ir3_get_image_coords(intr, NULL);
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ldib = ir3_LDIB(b, ir3_image_to_ibo(ctx, intr->src[0]), 0,
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ir3_create_collect(ctx, coords, ncoords), 0);
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ir3_create_collect(b, coords, ncoords), 0);
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ldib->dsts[0]->wrmask = MASK(intr->num_components);
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ldib->cat6.iim_val = intr->num_components;
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ldib->cat6.d = ncoords;
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@ -236,8 +236,8 @@ emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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/* src0 is offset, src1 is value:
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*/
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stib = ir3_STIB(b, ir3_image_to_ibo(ctx, intr->src[0]), 0,
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ir3_create_collect(ctx, coords, ncoords), 0,
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ir3_create_collect(ctx, value, ncomp), 0);
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ir3_create_collect(b, coords, ncoords), 0,
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ir3_create_collect(b, value, ncomp), 0);
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stib->cat6.iim_val = ncomp;
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stib->cat6.d = ncoords;
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stib->cat6.type = ir3_get_type_for_image_intrinsic(intr);
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@ -275,14 +275,14 @@ emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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* register) and then immediately extract the first component.
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*/
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dummy = create_immed(b, 0);
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src0 = ir3_create_collect(ctx, coords, ncoords);
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src0 = ir3_create_collect(b, coords, ncoords);
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if (intr->intrinsic == nir_intrinsic_image_atomic_comp_swap ||
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intr->intrinsic == nir_intrinsic_bindless_image_atomic_comp_swap) {
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struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[4])[0];
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src1 = ir3_collect(ctx, dummy, compare, value);
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src1 = ir3_collect(b, dummy, compare, value);
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} else {
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src1 = ir3_collect(ctx, dummy, value);
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src1 = ir3_collect(b, dummy, value);
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}
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switch (intr->intrinsic) {
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@ -372,7 +372,7 @@ emit_intrinsic_load_global_ir3(struct ir3_context *ctx,
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unsigned dest_components = nir_intrinsic_dest_components(intr);
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struct ir3_instruction *addr, *offset;
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addr = ir3_collect(ctx, ir3_get_src(ctx, &intr->src[0])[0],
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addr = ir3_collect(b, ir3_get_src(ctx, &intr->src[0])[0],
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ir3_get_src(ctx, &intr->src[0])[1]);
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offset = ir3_get_src(ctx, &intr->src[1])[0];
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@ -397,12 +397,12 @@ emit_intrinsic_store_global_ir3(struct ir3_context *ctx,
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struct ir3_instruction *value, *addr, *offset;
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unsigned ncomp = nir_intrinsic_src_components(intr, 0);
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addr = ir3_collect(ctx, ir3_get_src(ctx, &intr->src[1])[0],
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addr = ir3_collect(b, ir3_get_src(ctx, &intr->src[1])[0],
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ir3_get_src(ctx, &intr->src[1])[1]);
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offset = ir3_get_src(ctx, &intr->src[2])[0];
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value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
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value = ir3_create_collect(b, ir3_get_src(ctx, &intr->src[0]), ncomp);
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struct ir3_instruction *stg =
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ir3_STG_A(b, addr, 0, offset, 0, create_immed(b, 0), 0,
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@ -838,7 +838,7 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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carry->cat2.condition = IR3_COND_LT;
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base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
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addr = ir3_collect(ctx, addr, base_hi);
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addr = ir3_collect(b, addr, base_hi);
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}
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for (int i = 0; i < intr->num_components; i++) {
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@ -918,7 +918,7 @@ emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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assert(wrmask == BITFIELD_MASK(intr->num_components));
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stl = ir3_STL(b, offset, 0, ir3_create_collect(ctx, value, ncomp), 0,
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stl = ir3_STL(b, offset, 0, ir3_create_collect(b, value, ncomp), 0,
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create_immed(b, ncomp), 0);
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stl->cat6.dst_offset = base;
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stl->cat6.type = utype_src(intr->src[0]);
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@ -970,7 +970,7 @@ emit_intrinsic_store_shared_ir3(struct ir3_context *ctx,
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offset = ir3_get_src(ctx, &intr->src[1])[0];
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store = ir3_STLW(b, offset, 0,
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ir3_create_collect(ctx, value, intr->num_components), 0,
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ir3_create_collect(b, value, intr->num_components), 0,
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create_immed(b, intr->num_components), 0);
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/* for a650, use STL for vertex outputs used by tess ctrl shader: */
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@ -1044,7 +1044,7 @@ emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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break;
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case nir_intrinsic_shared_atomic_comp_swap:
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/* for cmpxchg, src1 is [ui]vec2(data, compare): */
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src1 = ir3_collect(ctx, ir3_get_src(ctx, &intr->src[2])[0], src1);
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src1 = ir3_collect(b, ir3_get_src(ctx, &intr->src[2])[0], src1);
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atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
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break;
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default:
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@ -1102,7 +1102,7 @@ emit_intrinsic_store_scratch(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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assert(wrmask == BITFIELD_MASK(intr->num_components));
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stp = ir3_STP(b, offset, 0, ir3_create_collect(ctx, value, ncomp), 0,
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stp = ir3_STP(b, offset, 0, ir3_create_collect(b, value, ncomp), 0,
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create_immed(b, ncomp), 0);
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stp->cat6.dst_offset = 0;
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stp->cat6.type = utype_src(intr->src[0]);
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@ -1166,7 +1166,7 @@ get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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texture = ir3_get_src(ctx, &intr->src[0])[0];
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sampler = create_immed(b, 0);
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info.samp_tex = ir3_collect(ctx, texture, sampler);
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info.samp_tex = ir3_collect(b, texture, sampler);
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}
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} else {
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info.flags |= IR3_INSTR_S2EN;
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@ -1177,7 +1177,7 @@ get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
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sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
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info.samp_tex = ir3_collect(ctx, sampler, texture);
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info.samp_tex = ir3_collect(b, sampler, texture);
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}
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return info;
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@ -1241,7 +1241,7 @@ emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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coords[ncoords++] = create_immed(b, 0);
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sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
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ir3_create_collect(ctx, coords, ncoords), NULL);
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ir3_create_collect(b, coords, ncoords), NULL);
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ir3_handle_nonuniform(sam, intr);
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@ -1506,7 +1506,7 @@ get_barycentric(struct ir3_context *ctx, enum ir3_bary bary)
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ij = create_sysval_input(ctx, sysval_base + bary, 0x3);
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ir3_split_dest(ctx->block, xy, ij, 0, 2);
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ctx->ij[bary] = ir3_create_collect(ctx, xy, 2);
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ctx->ij[bary] = ir3_create_collect(ctx->block, xy, 2);
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}
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return ctx->ij[bary];
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@ -1607,7 +1607,7 @@ get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
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}
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ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
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ctx->frag_coord = ir3_create_collect(b, xyzw, 4);
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}
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ctx->so->fragcoord_compmask |= nir_ssa_def_components_read(&intr->dest.ssa);
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@ -2343,7 +2343,7 @@ get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
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} else {
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sampler = create_immed(b, 0);
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}
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info.samp_tex = ir3_collect(ctx, texture, sampler);
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info.samp_tex = ir3_collect(b, texture, sampler);
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}
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} else {
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info.flags |= IR3_INSTR_S2EN;
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@ -2372,7 +2372,7 @@ get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
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info.samp_idx = tex->texture_index;
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}
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info.samp_tex = ir3_collect(ctx, sampler, texture);
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info.samp_tex = ir3_collect(b, sampler, texture);
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}
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return info;
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@ -2637,7 +2637,7 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
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ctx->so->fb_read = true;
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info.samp_tex = ir3_collect(
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ctx, create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
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b, create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
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create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16));
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info.flags = IR3_INSTR_S2EN;
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@ -2646,8 +2646,8 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
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info = get_tex_samp_tex_src(ctx, tex);
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}
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struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
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struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
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struct ir3_instruction *col0 = ir3_create_collect(b, src0, nsrc0);
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struct ir3_instruction *col1 = ir3_create_collect(b, src1, nsrc1);
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if (opc == OPC_META_TEX_PREFETCH) {
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int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
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@ -3318,7 +3318,7 @@ setup_input(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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struct ir3_instruction *coord = NULL;
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if (intr->intrinsic == nir_intrinsic_load_interpolated_input)
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coord = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), 2);
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coord = ir3_create_collect(ctx->block, ir3_get_src(ctx, &intr->src[0]), 2);
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compile_assert(ctx, nir_src_is_const(intr->src[coord ? 1 : 0]));
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@ -4019,7 +4019,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
|
|||
unsigned n = so->outputs_count++;
|
||||
so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
|
||||
|
||||
struct ir3_instruction *out = ir3_collect(ctx, ctx->primitive_id);
|
||||
struct ir3_instruction *out = ir3_collect(ctx->block, ctx->primitive_id);
|
||||
outputs[outputs_count] = out;
|
||||
outidxs[outputs_count] = n;
|
||||
if (so->type == MESA_SHADER_VERTEX && ctx->rel_patch_id)
|
||||
|
|
@ -4032,7 +4032,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
|
|||
if (so->type == MESA_SHADER_VERTEX && ctx->rel_patch_id) {
|
||||
unsigned n = so->outputs_count++;
|
||||
so->outputs[n].slot = VARYING_SLOT_REL_PATCH_ID_IR3;
|
||||
struct ir3_instruction *out = ir3_collect(ctx, ctx->rel_patch_id);
|
||||
struct ir3_instruction *out = ir3_collect(ctx->block, ctx->rel_patch_id);
|
||||
outputs[outputs_count] = out;
|
||||
outidxs[outputs_count] = n;
|
||||
regids[outputs_count] = regid(0, 1);
|
||||
|
|
@ -4042,7 +4042,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
|
|||
if (ctx->gs_header) {
|
||||
unsigned n = so->outputs_count++;
|
||||
so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
|
||||
struct ir3_instruction *out = ir3_collect(ctx, ctx->gs_header);
|
||||
struct ir3_instruction *out = ir3_collect(ctx->block, ctx->gs_header);
|
||||
outputs[outputs_count] = out;
|
||||
outidxs[outputs_count] = n;
|
||||
regids[outputs_count] = regid(0, 0);
|
||||
|
|
@ -4052,7 +4052,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
|
|||
if (ctx->tcs_header) {
|
||||
unsigned n = so->outputs_count++;
|
||||
so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
|
||||
struct ir3_instruction *out = ir3_collect(ctx, ctx->tcs_header);
|
||||
struct ir3_instruction *out = ir3_collect(ctx->block, ctx->tcs_header);
|
||||
outputs[outputs_count] = out;
|
||||
outidxs[outputs_count] = n;
|
||||
regids[outputs_count] = regid(0, 0);
|
||||
|
|
@ -4081,13 +4081,13 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
|
|||
struct ir3_instruction *outputs[ctx->noutputs / 4];
|
||||
unsigned outputs_count = 0;
|
||||
|
||||
struct ir3_block *old_block = ctx->block;
|
||||
struct ir3_block *b = ctx->block;
|
||||
/* Insert these collect's in the block before the end-block if
|
||||
* possible, so that any moves they generate can be shuffled around to
|
||||
* reduce nop's:
|
||||
*/
|
||||
if (ctx->block->predecessors_count == 1)
|
||||
ctx->block = ctx->block->predecessors[0];
|
||||
b = ctx->block->predecessors[0];
|
||||
|
||||
/* Setup IR level outputs, which are "collects" that gather
|
||||
* the scalar components of outputs.
|
||||
|
|
@ -4114,7 +4114,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
|
|||
continue;
|
||||
|
||||
struct ir3_instruction *out =
|
||||
ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
|
||||
ir3_create_collect(b, &ctx->outputs[i], ncomp);
|
||||
|
||||
int outidx = i / 4;
|
||||
assert(outidx < so->outputs_count);
|
||||
|
|
@ -4150,8 +4150,6 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
|
|||
}
|
||||
}
|
||||
|
||||
ctx->block = old_block;
|
||||
|
||||
struct ir3_instruction *end =
|
||||
ir3_instr_create(ctx->block, OPC_END, 0, outputs_count);
|
||||
|
||||
|
|
|
|||
|
|
@ -298,10 +298,9 @@ dest_flags(struct ir3_instruction *instr)
|
|||
}
|
||||
|
||||
struct ir3_instruction *
|
||||
ir3_create_collect(struct ir3_context *ctx, struct ir3_instruction *const *arr,
|
||||
ir3_create_collect(struct ir3_block *block, struct ir3_instruction *const *arr,
|
||||
unsigned arrsz)
|
||||
{
|
||||
struct ir3_block *block = ctx->block;
|
||||
struct ir3_instruction *collect;
|
||||
|
||||
if (arrsz == 0)
|
||||
|
|
@ -343,7 +342,7 @@ ir3_create_collect(struct ir3_context *ctx, struct ir3_instruction *const *arr,
|
|||
elem = ir3_MOV(block, elem, type);
|
||||
}
|
||||
|
||||
compile_assert(ctx, dest_flags(elem) == flags);
|
||||
debug_assert(dest_flags(elem) == flags);
|
||||
__ssa_src(collect, elem, flags);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -204,7 +204,7 @@ struct ir3_instruction **ir3_get_dst(struct ir3_context *ctx, nir_dest *dst,
|
|||
struct ir3_instruction *const *ir3_get_src(struct ir3_context *ctx,
|
||||
nir_src *src);
|
||||
void ir3_put_dst(struct ir3_context *ctx, nir_dest *dst);
|
||||
struct ir3_instruction *ir3_create_collect(struct ir3_context *ctx,
|
||||
struct ir3_instruction *ir3_create_collect(struct ir3_block *block,
|
||||
struct ir3_instruction *const *arr,
|
||||
unsigned arrsz);
|
||||
void ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst,
|
||||
|
|
@ -216,10 +216,10 @@ void emit_intrinsic_image_size_tex(struct ir3_context *ctx,
|
|||
nir_intrinsic_instr *intr,
|
||||
struct ir3_instruction **dst);
|
||||
|
||||
#define ir3_collect(ctx, ...) \
|
||||
#define ir3_collect(block, ...) \
|
||||
({ \
|
||||
struct ir3_instruction *__arr[] = {__VA_ARGS__}; \
|
||||
ir3_create_collect(ctx, __arr, ARRAY_SIZE(__arr)); \
|
||||
ir3_create_collect(block, __arr, ARRAY_SIZE(__arr)); \
|
||||
})
|
||||
|
||||
NORETURN void ir3_context_error(struct ir3_context *ctx, const char *format,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue