diff --git a/src/gallium/drivers/asahi/agx_pipe.c b/src/gallium/drivers/asahi/agx_pipe.c
index ffd7cf90c30..8cf5d31288a 100644
--- a/src/gallium/drivers/asahi/agx_pipe.c
+++ b/src/gallium/drivers/asahi/agx_pipe.c
@@ -1161,12 +1161,6 @@ transition_resource(struct pipe_context *pctx, struct agx_resource *rsrc,
    assert(new_res);
    assert(!(rsrc->base.bind & PIPE_BIND_SHARED) && "cannot swap BOs if shared");
 
-   /* Flush current writers out, so that rsrc->data_valid is correctly set (e.g.
-    * for render targets). The writers would have been flushed by the blits
-    * anyway, so this is not further harming performance.
-    */
-   agx_flush_writer(agx_context(pctx), rsrc, "Transition");
-
    int level;
    BITSET_FOREACH_SET(level, rsrc->data_valid, PIPE_MAX_TEXTURE_LEVELS) {
       /* Blit each valid level */
@@ -1305,24 +1299,8 @@ agx_flush_batch(struct agx_context *ctx, struct agx_batch *batch)
    for (unsigned i = 0; i < batch->key.nr_cbufs; ++i) {
       struct pipe_surface *surf = batch->key.cbufs[i];
 
-      if (surf && surf->texture) {
-         struct agx_resource *rt = agx_resource(surf->texture);
-         BITSET_SET(rt->data_valid, surf->u.tex.level);
-
-         if (!(batch->clear & (PIPE_CLEAR_COLOR0 << i)))
-            clear_pipeline_textures = true;
-      }
-   }
-
-   struct agx_resource *zbuf =
-      batch->key.zsbuf ? agx_resource(batch->key.zsbuf->texture) : NULL;
-
-   if (zbuf) {
-      unsigned level = batch->key.zsbuf->u.tex.level;
-      BITSET_SET(zbuf->data_valid, level);
-
-      if (zbuf->separate_stencil)
-         BITSET_SET(zbuf->separate_stencil->data_valid, level);
+      clear_pipeline_textures |=
+         surf && surf->texture && !(batch->clear & (PIPE_CLEAR_COLOR0 << i));
    }
 
    /* Scissor and depth bias arrays are staged to dynamic arrays on the CPU. At
diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c
index 19d8ce9a26f..045a7869eb0 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -31,6 +31,7 @@
 #include "pipe/p_defines.h"
 #include "pipe/p_screen.h"
 #include "pipe/p_state.h"
+#include "util/bitset.h"
 #include "util/blob.h"
 #include "util/compiler.h"
 #include "util/format/u_format.h"
@@ -2810,8 +2811,7 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
           */
          key.op[rt] = AGX_META_OP_NONE;
       } else {
-         struct agx_resource *rsrc = agx_resource(surf->texture);
-         bool valid = agx_resource_valid(rsrc, surf->u.tex.level);
+         bool valid = (batch->load & (PIPE_CLEAR_COLOR0 << rt));
          bool clear = (batch->clear & (PIPE_CLEAR_COLOR0 << rt));
          bool load = valid && !clear;
 
@@ -3082,16 +3082,29 @@ agx_batch_init_state(struct agx_batch *batch)
    }
 
    if (batch->key.zsbuf) {
+      unsigned level = batch->key.zsbuf->u.tex.level;
       struct agx_resource *rsrc = agx_resource(batch->key.zsbuf->texture);
-      agx_batch_writes(batch, rsrc);
 
-      if (rsrc->separate_stencil)
+      agx_batch_writes(batch, rsrc);
+      BITSET_SET(rsrc->data_valid, level);
+
+      if (rsrc->separate_stencil) {
          agx_batch_writes(batch, rsrc->separate_stencil);
+         BITSET_SET(rsrc->separate_stencil->data_valid, level);
+      }
    }
 
    for (unsigned i = 0; i < batch->key.nr_cbufs; ++i) {
-      if (batch->key.cbufs[i])
-         agx_batch_writes(batch, agx_resource(batch->key.cbufs[i]->texture));
+      if (batch->key.cbufs[i]) {
+         struct agx_resource *rsrc = agx_resource(batch->key.cbufs[i]->texture);
+         unsigned level = batch->key.cbufs[i]->u.tex.level;
+
+         if (agx_resource_valid(rsrc, level))
+            batch->load |= PIPE_CLEAR_COLOR0 << i;
+
+         agx_batch_writes(batch, rsrc);
+         BITSET_SET(rsrc->data_valid, batch->key.cbufs[i]->u.tex.level);
+      }
    }
 
    /* Set up standard sample positions */