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gallium: rename PIPE_.._PIN_THREADS_TO_L3_CACHE -> .._UPDATE_THREAD_SCHEDULING

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Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27247>
This commit is contained in:
Marek Olšák 2024-01-17 08:25:04 -05:00 • committed by Marge Bot
parent d230434ae3
commit 386822c1b0
6 changed files with 8 additions and 11 deletions
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2
src/gallium/auxiliary/util/u_threaded_context.c
View file

@ -3552,7 +3552,7 @@ tc_set_context_param(struct pipe_context *_pipe,
{
struct threaded_context *tc = threaded_context(_pipe);
if (param == PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE) {
if (param == PIPE_CONTEXT_PARAM_UPDATE_THREAD_SCHEDULING) {
util_thread_sched_apply_policy(tc->queue.threads[0],
UTIL_THREAD_THREADED_CONTEXT, value,
NULL);

2
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -470,7 +470,7 @@ static void si_set_context_param(struct pipe_context *ctx, enum pipe_context_par
struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
switch (param) {
case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
case PIPE_CONTEXT_PARAM_UPDATE_THREAD_SCHEDULING:
ws->pin_threads_to_L3_cache(ws, value);
break;
default:;

2
src/gallium/drivers/zink/zink_context.c
View file

@ -329,7 +329,7 @@ zink_set_context_param(struct pipe_context *pctx, enum pipe_context_param param,
struct zink_screen *screen = zink_screen(ctx->base.screen);
switch (param) {
case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
case PIPE_CONTEXT_PARAM_UPDATE_THREAD_SCHEDULING:
if (screen->threaded_submit)
util_thread_sched_apply_policy(screen->flush_queue.threads[0],
UTIL_THREAD_DRIVER_SUBMIT, value, NULL);

9
src/gallium/include/pipe/p_defines.h
View file

@ -1101,13 +1101,10 @@ enum pipe_resource_param
*/
enum pipe_context_param
{
/* A hint for the driver that it should pin its execution threads to
* a group of cores sharing a specific L3 cache if the CPU has multiple
* L3 caches. This is needed for good multithreading performance on
* AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have
* any internal threads or don't run on affected CPUs can ignore this.
/* Call util_thread_sched_apply_policy() for each driver thread that
* benefits from it.
*/
PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
PIPE_CONTEXT_PARAM_UPDATE_THREAD_SCHEDULING,
};
/**

2
src/mesa/main/glthread.c
View file

@ -334,7 +334,7 @@ _mesa_glthread_flush_batch(struct gl_context *ctx)
&glthread->thread_sched_state)) {
/* If it's successful, apply the policy to the driver threads too. */
ctx->pipe->set_context_param(ctx->pipe,
PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
PIPE_CONTEXT_PARAM_UPDATE_THREAD_SCHEDULING,
cpu);
}
}

2
src/mesa/state_tracker/st_draw.c
View file

@ -104,7 +104,7 @@ st_prepare_draw(struct gl_context *ctx, uint64_t state_mask)
if (L3_cache != U_CPU_INVALID_L3) {
pipe->set_context_param(pipe,
PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
PIPE_CONTEXT_PARAM_UPDATE_THREAD_SCHEDULING,
cpu);
}
}