diff --git a/src/compiler/isaspec/encode.py b/src/compiler/isaspec/encode.py
index 62e4ff934b5..a800cf3b16f 100755
--- a/src/compiler/isaspec/encode.py
+++ b/src/compiler/isaspec/encode.py
@@ -437,7 +437,7 @@ pack_field(unsigned low, unsigned high, int64_t val, bool is_signed)
  */
 
 %for root in s.encode_roots():
-static bitmask_t encode${root.get_c_name()}(struct encode_state *s, struct bitset_params *p, ${root.encode.type} src);
+static bitmask_t encode${root.get_c_name()}(struct encode_state *s, struct bitset_params *p, const ${root.encode.type} src);
 %endfor
 
 ## TODO before the expr evaluators, we should generate extract_FOO() for
@@ -465,7 +465,7 @@ struct bitset_params {
 
 <%def name="render_expr(leaf, expr)">
 static inline int64_t
-${s.expr_name(leaf.get_root(), expr)}(struct encode_state *s, struct bitset_params *p, ${leaf.get_root().encode.type} src)
+${s.expr_name(leaf.get_root(), expr)}(struct encode_state *s, struct bitset_params *p, const ${leaf.get_root().encode.type} src)
 {
 %   for fieldname in expr.fieldnames:
     int64_t ${fieldname};
@@ -491,7 +491,7 @@ ${s.expr_name(leaf.get_root(), expr)}(struct encode_state *s, struct bitset_para
 %for root in s.encode_roots():
 %   for leaf in s.encode_leafs(root):
 %      for expr in s.bitset_used_exprs(leaf):
-static inline int64_t ${s.expr_name(leaf.get_root(), expr)}(struct encode_state *s, struct bitset_params *p, ${leaf.get_root().encode.type} src);
+static inline int64_t ${s.expr_name(leaf.get_root(), expr)}(struct encode_state *s, struct bitset_params *p, const ${leaf.get_root().encode.type} src);
 %      endfor
 %   endfor
 %endfor
@@ -523,7 +523,7 @@ static inline int64_t ${s.expr_name(leaf.get_root(), expr)}(struct encode_state
 %      if snippet not in root.snippets.keys():
 <% snippet_name = "snippet" + root.get_c_name() + "_" + str(len(root.snippets)) %>
 static bitmask_t
-${snippet_name}(struct encode_state *s, struct bitset_params *p, ${root.encode.type} src)
+${snippet_name}(struct encode_state *s, struct bitset_params *p, const ${root.encode.type} src)
 {
    bitmask_t val = uint64_t_to_bitmask(0);
 ${snippet}
@@ -534,7 +534,7 @@ ${snippet}
 %   endfor
 
 static bitmask_t
-encode${root.get_c_name()}(struct encode_state *s, struct bitset_params *p, ${root.encode.type} src)
+encode${root.get_c_name()}(struct encode_state *s, struct bitset_params *p, const ${root.encode.type} src)
 {
 %   if root.encode.case_prefix is not None:
    switch (${root.get_c_name()}_case(s, src)) {
diff --git a/src/freedreno/afuc/asm.c b/src/freedreno/afuc/asm.c
index 71d693dd71c..45497b25c23 100644
--- a/src/freedreno/afuc/asm.c
+++ b/src/freedreno/afuc/asm.c
@@ -45,7 +45,7 @@ struct encode_state {
 };
 
 static afuc_opc
-__instruction_case(struct encode_state *s, struct afuc_instr *instr)
+__instruction_case(struct encode_state *s, const struct afuc_instr *instr)
 {
    switch (instr->opc) {
 #define ALU(name) \
diff --git a/src/freedreno/isa/encode.c b/src/freedreno/isa/encode.c
index 025798577bb..441fff1eb52 100644
--- a/src/freedreno/isa/encode.c
+++ b/src/freedreno/isa/encode.c
@@ -49,7 +49,7 @@ struct encode_state {
  */
 
 static inline bool
-extract_SRC1_R(struct ir3_instruction *instr)
+extract_SRC1_R(const struct ir3_instruction *instr)
 {
 	if (instr->nop) {
 		assert(!instr->repeat);
@@ -59,7 +59,7 @@ extract_SRC1_R(struct ir3_instruction *instr)
 }
 
 static inline bool
-extract_SRC2_R(struct ir3_instruction *instr)
+extract_SRC2_R(const struct ir3_instruction *instr)
 {
 	if (instr->nop) {
 		assert(!instr->repeat);
@@ -72,7 +72,7 @@ extract_SRC2_R(struct ir3_instruction *instr)
 }
 
 static inline opc_t
-__instruction_case(struct encode_state *s, struct ir3_instruction *instr)
+__instruction_case(struct encode_state *s, const struct ir3_instruction *instr)
 {
 	/*
 	 * Temporary hack.. the new world doesn't map opcodes directly to hw
@@ -112,7 +112,7 @@ __instruction_case(struct encode_state *s, struct ir3_instruction *instr)
 }
 
 static inline unsigned
-extract_ABSNEG(struct ir3_register *reg)
+extract_ABSNEG(const struct ir3_register *reg)
 {
 	// TODO generate enums for this:
 	if (reg->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT)) {
@@ -129,14 +129,14 @@ extract_ABSNEG(struct ir3_register *reg)
 }
 
 static inline int32_t
-extract_reg_iim(struct ir3_register *reg)
+extract_reg_iim(const struct ir3_register *reg)
 {
    assert(reg->flags & IR3_REG_IMMED);
    return reg->iim_val;
 }
 
 static inline uint32_t
-extract_reg_uim(struct ir3_register *reg)
+extract_reg_uim(const struct ir3_register *reg)
 {
    assert(reg->flags & IR3_REG_IMMED);
    return reg->uim_val;
@@ -149,7 +149,7 @@ extract_reg_uim(struct ir3_register *reg)
  * TODO revisit this once legacy 'packed struct' encoding is gone
  */
 static inline struct ir3_register *
-extract_cat5_SRC(struct ir3_instruction *instr, unsigned n)
+extract_cat5_SRC(const struct ir3_instruction *instr, unsigned n)
 {
 	if (instr->flags & IR3_INSTR_S2EN) {
 		n++;
@@ -160,7 +160,7 @@ extract_cat5_SRC(struct ir3_instruction *instr, unsigned n)
 }
 
 static inline bool
-extract_cat5_FULL(struct ir3_instruction *instr)
+extract_cat5_FULL(const struct ir3_instruction *instr)
 {
 	struct ir3_register *reg = extract_cat5_SRC(instr, 0);
 	/* some cat5 have zero src regs, in which case 'FULL' is false */
@@ -170,7 +170,7 @@ extract_cat5_FULL(struct ir3_instruction *instr)
 }
 
 static inline cat5_desc_mode_t
-extract_cat5_DESC_MODE(struct ir3_instruction *instr)
+extract_cat5_DESC_MODE(const struct ir3_instruction *instr)
 {
 	assert(instr->flags & (IR3_INSTR_S2EN | IR3_INSTR_B));
 	if (instr->flags & IR3_INSTR_S2EN) {
@@ -204,7 +204,7 @@ extract_cat5_DESC_MODE(struct ir3_instruction *instr)
 }
 
 static inline unsigned
-extract_cat6_DESC_MODE(struct ir3_instruction *instr)
+extract_cat6_DESC_MODE(const struct ir3_instruction *instr)
 {
 	struct ir3_register *ssbo = instr->srcs[0];
 	if (ssbo->flags & IR3_REG_IMMED) {
@@ -224,7 +224,7 @@ extract_cat6_DESC_MODE(struct ir3_instruction *instr)
  * TODO revisit this once legacy 'packed struct' encoding is gone
  */
 static inline struct ir3_register *
-extract_cat6_SRC(struct ir3_instruction *instr, unsigned n)
+extract_cat6_SRC(const struct ir3_instruction *instr, unsigned n)
 {
 	if (is_global_a3xx_atomic(instr->opc)) {
 		n++;
@@ -244,7 +244,7 @@ typedef enum {
 } reg_multisrc_t;
 
 static inline reg_multisrc_t
-__multisrc_case(struct encode_state *s, struct ir3_register *reg)
+__multisrc_case(struct encode_state *s, const struct ir3_register *reg)
 {
 	if (reg->flags & IR3_REG_IMMED) {
 		assert(opc_cat(s->instr->opc) == 2);
@@ -276,7 +276,7 @@ typedef enum {
 } reg_cat3_src_t;
 
 static inline reg_cat3_src_t
-__cat3_src_case(struct encode_state *s, struct ir3_register *reg)
+__cat3_src_case(struct encode_state *s, const struct ir3_register *reg)
 {
 	if (reg->flags & IR3_REG_RELATIV) {
 		if (reg->flags & IR3_REG_CONST) {
@@ -297,7 +297,7 @@ typedef enum {
 } stc_dst_t;
 
 static inline stc_dst_t
-__const_dst_case(struct encode_state *s, struct ir3_instruction *instr)
+__const_dst_case(struct encode_state *s, const struct ir3_instruction *instr)
 {
    return (instr->flags & IR3_INSTR_A1EN) ? CONST_DST_A1 : CONST_DST_IMM;
 }