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aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7

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GFX6-7 are affected by a hw bug that prevents address clamping to work
correctly when the SGPR offset is used. Use the VGPR offset to fix it.

Fixes various hangs with dEQP-VK.robustness.robustness2.* on Bonaire.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11238>
This commit is contained in:
Samuel Pitoiset 2021-06-07 15:19:59 +02:00 • committed by Marge Bot
parent d523126bd0
commit 3761d994f6
2 changed files with 19 additions and 0 deletions
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6
src/amd/compiler/README-ISA.md
View file

@ -160,6 +160,12 @@ finish and then write to vcc (for example, `s_mov_b64 vcc, vcc`) to correct vccz
Currently, we don't do this.
## SGPR offset on MUBUF prevents addr clamping on SI/CI
[See this LLVM source.](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp#L1917-L1922)
This leads to wrong bounds checking, using a VGPR offset fixes it.
## GCN / GFX6 hazards
### VINTRP followed by a read with `v_readfirstlane` or `v_readlane`

13
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -5066,6 +5066,13 @@ void load_buffer(isel_context *ctx, unsigned num_components, unsigned component_
bool use_smem = dst.type() != RegType::vgpr && (!glc || ctx->options->chip_class >= GFX8) && allow_smem;
if (use_smem)
offset = bld.as_uniform(offset);
else {
/* GFX6-7 are affected by a hw bug that prevents address clamping to
* work correctly when the SGPR offset is used.
*/
if (offset.type() == RegType::sgpr && ctx->options->chip_class < GFX8)
offset = as_vgpr(ctx, offset);
}
LoadEmitInfo info = {Operand(offset), dst, num_components, component_size, rsrc};
info.glc = glc;
@ -6316,6 +6323,12 @@ void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
split_buffer_store(ctx, instr, false, RegType::vgpr,
data, writemask, 16, &write_count, write_datas, offsets);
/* GFX6-7 are affected by a hw bug that prevents address clamping to work
* correctly when the SGPR offset is used.
*/
if (offset.type() == RegType::sgpr && ctx->options->chip_class < GFX8)
offset = as_vgpr(ctx, offset);
for (unsigned i = 0; i < write_count; i++) {
aco_opcode op = get_buffer_store_op(write_datas[i].bytes());