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r600/sfn: Don't tag mem-ring and stream instructions as exports

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Export instructions allow burst writes, so it makes send to try
to allocate consecutive registers, but for ring writes we don't
schedule the outputs correctly to exploit this, so for now
don't mark these instructions as export to let the RA restart
picking colors.

When the scheduler starts to emit the ring writes in the right order
to allow for bust writes we might revisit this.

This fixes
  spec@glsl-1.50@execution@variable-indexing@gs-output-array-vec4-index-wr

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit fd71cd0b6a)
This commit is contained in:
Gert Wollny 2022-08-23 15:03:48 +02:00 • committed by Dylan Baker
parent 7bcd2e6767
commit 36a66a3124
3 changed files with 4 additions and 4 deletions
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2
.pick_status.json
View file

@ -10318,7 +10318,7 @@
"description": "r600/sfn: Don't tag mem-ring and stream instructions as exports",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "79ca456b4837b3bc21cf9ef3c03c505c4b4909f6"
},

4
src/gallium/drivers/r600/sfn/sfn_liverangeevaluator.cpp
View file

@ -308,14 +308,14 @@ void LiveRangeInstrVisitor::visit(StreamOutInstr *instr)
{
sfn_log << SfnLog::merge << "Visit " << *instr << "\n";
auto src = instr->value();
record_read(src, LiveRangeEntry::use_export);
record_read(src, LiveRangeEntry::use_unspecified);
}
void LiveRangeInstrVisitor::visit(MemRingOutInstr *instr)
{
sfn_log << SfnLog::merge << "Visit " << *instr << "\n";
auto src = instr->value();
record_read(src, LiveRangeEntry::use_export);
record_read(src, LiveRangeEntry::use_unspecified);
auto idx = instr->export_index();
if (idx && idx->as_register())

2
src/gallium/drivers/r600/sfn/sfn_scheduler.cpp
View file

@ -329,7 +329,7 @@ void BlockSheduler::schedule_block(Block& in_block, Shader::ShaderBlocks& out_bl
if (!m_current_block->lds_group_active()) {
if (last_shed != sched_free && memops_ready.size() > 8)
current_shed = sched_free;
else if (mem_ring_writes_ready.size() > 5)
else if (mem_ring_writes_ready.size() > 15)
current_shed = sched_mem_ring;
else if (rat_instr_ready.size() > 3)
current_shed = sched_rat;