mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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i965; Move brw_meta_get_*_rect to brw_meta_util.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Jason Ekstrand
parent
21034f1b08
commit
36529f670f
2 changed files with 180 additions and 180 deletions
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@ -216,149 +216,6 @@ brw_draw_rectlist(struct brw_context *brw, struct rect *rect, int num_instances)
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NULL, 0, NULL);
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}
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void
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brw_get_fast_clear_rect(const struct brw_context *brw,
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const struct gl_framebuffer *fb,
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const struct intel_mipmap_tree* mt,
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unsigned *x0, unsigned *y0,
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unsigned *x1, unsigned *y1)
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{
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unsigned int x_align, y_align;
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unsigned int x_scaledown, y_scaledown;
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/* Only single sampled surfaces need to (and actually can) be resolved. */
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if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE ||
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intel_miptree_is_lossless_compressed(brw, mt)) {
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p327):
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*
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* Clear pass must have a clear rectangle that must follow
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* alignment rules in terms of pixels and lines as shown in the
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* table below. Further, the clear-rectangle height and width
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* must be multiple of the following dimensions. If the height
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* and width of the render target being cleared do not meet these
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* requirements, an MCS buffer can be created such that it
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* follows the requirement and covers the RT.
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*
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* The alignment size in the table that follows is related to the
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* alignment size returned by intel_get_non_msrt_mcs_alignment(), but
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* with X alignment multiplied by 16 and Y alignment multiplied by 32.
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*/
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intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
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x_align *= 16;
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/* SKL+ line alignment requirement for Y-tiled are half those of the prior
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* generations.
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*/
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if (brw->gen >= 9)
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y_align *= 16;
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else
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y_align *= 32;
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p327):
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*
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* In order to optimize the performance MCS buffer (when bound to
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* 1X RT) clear similarly to MCS buffer clear for MSRT case,
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* clear rect is required to be scaled by the following factors
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* in the horizontal and vertical directions:
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*
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* The X and Y scale down factors in the table that follows are each
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* equal to half the alignment value computed above.
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*/
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x_scaledown = x_align / 2;
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y_scaledown = y_align / 2;
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/* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
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* Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
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* Clear of Non-MultiSampled Render Target Restrictions":
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*
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* Clear rectangle must be aligned to two times the number of
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* pixels in the table shown below due to 16x16 hashing across the
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* slice.
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*/
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x_align *= 2;
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y_align *= 2;
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} else {
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "MSAA Compression" bullet (p326):
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*
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* Clear pass for this case requires that scaled down primitive
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* is sent down with upper left co-ordinate to coincide with
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* actual rectangle being cleared. For MSAA, clear rectangle’s
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* height and width need to as show in the following table in
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* terms of (width,height) of the RT.
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*
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* MSAA Width of Clear Rect Height of Clear Rect
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* 2X Ceil(1/8*width) Ceil(1/2*height)
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* 4X Ceil(1/8*width) Ceil(1/2*height)
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* 8X Ceil(1/2*width) Ceil(1/2*height)
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* 16X width Ceil(1/2*height)
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*
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* The text "with upper left co-ordinate to coincide with actual
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* rectangle being cleared" is a little confusing--it seems to imply
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* that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
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* feed the pipeline using the rectangle (x,y) to
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* (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
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* the number of samples. Experiments indicate that this is not
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* quite correct; actually, what the hardware appears to do is to
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* align whatever rectangle is sent down the pipeline to the nearest
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* multiple of 2x2 blocks, and then scale it up by a factor of N
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* horizontally and 2 vertically. So the resulting alignment is 4
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* vertically and either 4 or 16 horizontally, and the scaledown
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* factor is 2 vertically and either 2 or 8 horizontally.
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*/
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switch (mt->num_samples) {
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case 2:
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case 4:
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x_scaledown = 8;
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break;
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case 8:
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x_scaledown = 2;
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break;
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case 16:
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x_scaledown = 1;
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break;
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default:
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unreachable("Unexpected sample count for fast clear");
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}
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y_scaledown = 2;
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x_align = x_scaledown * 2;
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y_align = y_scaledown * 2;
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}
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*x0 = fb->_Xmin;
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*x1 = fb->_Xmax;
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if (fb->Name != 0) {
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*y0 = fb->_Ymin;
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*y1 = fb->_Ymax;
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} else {
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*y0 = fb->Height - fb->_Ymax;
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*y1 = fb->Height - fb->_Ymin;
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}
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*x0 = ROUND_DOWN_TO(*x0, x_align) / x_scaledown;
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*y0 = ROUND_DOWN_TO(*y0, y_align) / y_scaledown;
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*x1 = ALIGN(*x1, x_align) / x_scaledown;
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*y1 = ALIGN(*y1, y_align) / y_scaledown;
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}
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void
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brw_meta_get_buffer_rect(const struct gl_framebuffer *fb,
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unsigned *x0, unsigned *y0,
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unsigned *x1, unsigned *y1)
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{
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*x0 = fb->_Xmin;
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*x1 = fb->_Xmax;
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if (fb->Name != 0) {
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*y0 = fb->_Ymin;
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*y1 = fb->_Ymax;
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} else {
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*y0 = fb->Height - fb->_Ymax;
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*y1 = fb->Height - fb->_Ymin;
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}
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}
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/**
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* Convert the given color to a bitfield suitable for ORing into DWORD 7 of
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* SURFACE_STATE (DWORD 12-15 on SKL+).
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@ -769,43 +626,6 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
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return true;
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}
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void
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brw_get_resolve_rect(const struct brw_context *brw,
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const struct intel_mipmap_tree *mt,
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unsigned *x0, unsigned *y0,
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unsigned *x1, unsigned *y1)
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{
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unsigned x_align, y_align;
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unsigned x_scaledown, y_scaledown;
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/* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
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*
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* A rectangle primitive must be scaled down by the following factors
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* with respect to render target being resolved.
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*
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* The scaledown factors in the table that follows are related to the
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* alignment size returned by intel_get_non_msrt_mcs_alignment() by a
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* multiplier. For IVB and HSW, we divide by two, for BDW we multiply
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* by 8 and 16. Similar to the fast clear, SKL eases the BDW vertical scaling
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* by a factor of 2.
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*/
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intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
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if (brw->gen >= 9) {
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x_scaledown = x_align * 8;
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y_scaledown = y_align * 8;
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} else if (brw->gen >= 8) {
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x_scaledown = x_align * 8;
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y_scaledown = y_align * 16;
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} else {
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x_scaledown = x_align / 2;
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y_scaledown = y_align / 2;
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}
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*x0 = *y0 = 0;
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*x1 = ALIGN(mt->logical_width0, x_scaledown) / x_scaledown;
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*y1 = ALIGN(mt->logical_height0, y_scaledown) / y_scaledown;
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}
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void
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brw_meta_resolve_color(struct brw_context *brw,
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struct intel_mipmap_tree *mt)
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@ -366,3 +366,183 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
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}
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return true;
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}
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void
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brw_get_fast_clear_rect(const struct brw_context *brw,
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const struct gl_framebuffer *fb,
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const struct intel_mipmap_tree* mt,
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unsigned *x0, unsigned *y0,
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unsigned *x1, unsigned *y1)
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{
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unsigned int x_align, y_align;
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unsigned int x_scaledown, y_scaledown;
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/* Only single sampled surfaces need to (and actually can) be resolved. */
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if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE ||
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intel_miptree_is_lossless_compressed(brw, mt)) {
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p327):
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*
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* Clear pass must have a clear rectangle that must follow
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* alignment rules in terms of pixels and lines as shown in the
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* table below. Further, the clear-rectangle height and width
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* must be multiple of the following dimensions. If the height
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* and width of the render target being cleared do not meet these
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* requirements, an MCS buffer can be created such that it
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* follows the requirement and covers the RT.
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*
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* The alignment size in the table that follows is related to the
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* alignment size returned by intel_get_non_msrt_mcs_alignment(), but
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* with X alignment multiplied by 16 and Y alignment multiplied by 32.
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*/
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intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
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x_align *= 16;
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/* SKL+ line alignment requirement for Y-tiled are half those of the prior
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* generations.
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*/
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if (brw->gen >= 9)
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y_align *= 16;
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else
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y_align *= 32;
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p327):
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*
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* In order to optimize the performance MCS buffer (when bound to
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* 1X RT) clear similarly to MCS buffer clear for MSRT case,
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* clear rect is required to be scaled by the following factors
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* in the horizontal and vertical directions:
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*
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* The X and Y scale down factors in the table that follows are each
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* equal to half the alignment value computed above.
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*/
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x_scaledown = x_align / 2;
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y_scaledown = y_align / 2;
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/* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
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* Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
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* Clear of Non-MultiSampled Render Target Restrictions":
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*
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* Clear rectangle must be aligned to two times the number of
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* pixels in the table shown below due to 16x16 hashing across the
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* slice.
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*/
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x_align *= 2;
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y_align *= 2;
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} else {
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "MSAA Compression" bullet (p326):
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*
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* Clear pass for this case requires that scaled down primitive
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* is sent down with upper left co-ordinate to coincide with
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* actual rectangle being cleared. For MSAA, clear rectangle’s
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* height and width need to as show in the following table in
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* terms of (width,height) of the RT.
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*
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* MSAA Width of Clear Rect Height of Clear Rect
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* 2X Ceil(1/8*width) Ceil(1/2*height)
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* 4X Ceil(1/8*width) Ceil(1/2*height)
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* 8X Ceil(1/2*width) Ceil(1/2*height)
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* 16X width Ceil(1/2*height)
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*
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* The text "with upper left co-ordinate to coincide with actual
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* rectangle being cleared" is a little confusing--it seems to imply
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* that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
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* feed the pipeline using the rectangle (x,y) to
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* (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
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* the number of samples. Experiments indicate that this is not
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* quite correct; actually, what the hardware appears to do is to
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* align whatever rectangle is sent down the pipeline to the nearest
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* multiple of 2x2 blocks, and then scale it up by a factor of N
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* horizontally and 2 vertically. So the resulting alignment is 4
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* vertically and either 4 or 16 horizontally, and the scaledown
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* factor is 2 vertically and either 2 or 8 horizontally.
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*/
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switch (mt->num_samples) {
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case 2:
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case 4:
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x_scaledown = 8;
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break;
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case 8:
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x_scaledown = 2;
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break;
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case 16:
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x_scaledown = 1;
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break;
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default:
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unreachable("Unexpected sample count for fast clear");
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}
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y_scaledown = 2;
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x_align = x_scaledown * 2;
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y_align = y_scaledown * 2;
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}
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*x0 = fb->_Xmin;
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*x1 = fb->_Xmax;
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if (fb->Name != 0) {
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*y0 = fb->_Ymin;
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*y1 = fb->_Ymax;
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} else {
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*y0 = fb->Height - fb->_Ymax;
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*y1 = fb->Height - fb->_Ymin;
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}
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*x0 = ROUND_DOWN_TO(*x0, x_align) / x_scaledown;
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*y0 = ROUND_DOWN_TO(*y0, y_align) / y_scaledown;
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*x1 = ALIGN(*x1, x_align) / x_scaledown;
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*y1 = ALIGN(*y1, y_align) / y_scaledown;
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}
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void
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brw_meta_get_buffer_rect(const struct gl_framebuffer *fb,
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unsigned *x0, unsigned *y0,
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unsigned *x1, unsigned *y1)
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{
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*x0 = fb->_Xmin;
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*x1 = fb->_Xmax;
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if (fb->Name != 0) {
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*y0 = fb->_Ymin;
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*y1 = fb->_Ymax;
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} else {
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*y0 = fb->Height - fb->_Ymax;
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*y1 = fb->Height - fb->_Ymin;
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}
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}
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void
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brw_get_resolve_rect(const struct brw_context *brw,
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const struct intel_mipmap_tree *mt,
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unsigned *x0, unsigned *y0,
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unsigned *x1, unsigned *y1)
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{
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unsigned x_align, y_align;
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unsigned x_scaledown, y_scaledown;
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/* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
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*
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* A rectangle primitive must be scaled down by the following factors
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* with respect to render target being resolved.
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*
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* The scaledown factors in the table that follows are related to the
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* alignment size returned by intel_get_non_msrt_mcs_alignment() by a
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* multiplier. For IVB and HSW, we divide by two, for BDW we multiply
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* by 8 and 16. Similar to the fast clear, SKL eases the BDW vertical scaling
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* by a factor of 2.
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*/
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intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
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if (brw->gen >= 9) {
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x_scaledown = x_align * 8;
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y_scaledown = y_align * 8;
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} else if (brw->gen >= 8) {
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x_scaledown = x_align * 8;
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y_scaledown = y_align * 16;
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} else {
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x_scaledown = x_align / 2;
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y_scaledown = y_align / 2;
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}
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*x0 = *y0 = 0;
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*x1 = ALIGN(mt->logical_width0, x_scaledown) / x_scaledown;
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*y1 = ALIGN(mt->logical_height0, y_scaledown) / y_scaledown;
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}
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