diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 010894d53be..370f98b811d 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -125,6 +125,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
 #if GFX_VERx10 >= 125
       db.TiledMode = isl_encode_tiling[info->depth_surf->tiling];
       db.MipTailStartLOD = 15;
+      db.CompressionMode = isl_aux_usage_has_ccs(info->hiz_usage);
+      db.RenderCompressionFormat =
+         isl_get_render_compression_format(info->depth_surf->format);
 #elif GFX_VER <= 6
       db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR;
       db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
@@ -169,6 +172,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
 #if GFX_VERx10 >= 125
       sb.TiledMode = isl_encode_tiling[info->stencil_surf->tiling];
       sb.MipTailStartLOD = 15;
+      sb.CompressionMode = isl_aux_usage_has_ccs(info->stencil_aux_usage);
+      sb.RenderCompressionFormat =
+         isl_get_render_compression_format(info->stencil_surf->format);
 #endif
 #if GFX_VER >= 12
       sb.StencilWriteEnable = true;
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 40415bd3b92..dbbf2de8942 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -705,6 +705,10 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
          }
       }
 
+#if GFX_VERx10 >= 125
+      s.RenderCompressionFormat =
+         isl_get_render_compression_format(info->surf->format);
+#endif
 #if GFX_VER >= 12
       s.MemoryCompressionEnable = info->aux_usage == ISL_AUX_USAGE_MC;
 #endif