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iris/gfx12.5: Apply HIZ-CCS resolve DC flush after full resolves for all gfx12.5.

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This appears to be needed to guarantee that a resolved depth surface
has no remaining fast-cleared blocks on DG2 as well as MTL.  After
this series this should no longer be hit in practice since we'll be
doing partial resolves in most cases, but it seems sensible to keep
and correct the workaround for our peace of mind to make sure that
full resolves are truly resolving the main surface.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31139>
This commit is contained in:
Francisco Jerez 2025-01-23 16:10:23 -08:00 • committed by Marge Bot
parent 349b09f8a2
commit 35512cebb1
1 changed files with 17 additions and 8 deletions
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25
src/gallium/drivers/iris/iris_resolve.c
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@ -696,13 +696,6 @@ iris_hiz_exec(struct iris_context *ice,
//DBG("%s %s to mt %p level %d layers %d-%d\n",
//__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
/* A data cache flush is not suggested by HW docs, but we found it to fix
* a number of failures.
*/
unsigned wa_flush = devinfo->verx10 >= 125 &&
res->aux.usage == ISL_AUX_USAGE_HIZ_CCS ?
PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
/* The following stalls and flushes are only documented to be required
* for HiZ clear operations. However, they also seem to be required for
* resolve operations.
@ -719,7 +712,6 @@ iris_hiz_exec(struct iris_context *ice,
iris_emit_pipe_control_flush(batch,
"hiz op: pre-flush",
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
wa_flush |
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_CS_STALL);
@ -764,6 +756,23 @@ iris_hiz_exec(struct iris_context *ice,
PIPE_CONTROL_DEPTH_STALL);
}
/* Additional tile cache flush which appears to be needed to
* guarantee that a resolved depth surface has no remaining
* fast-cleared blocks on DG2 as well as MTL:
*
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/10420
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/10530
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/11315
*/
if (devinfo->verx10 == 125 &&
res->aux.usage == ISL_AUX_USAGE_HIZ_CCS &&
op == ISL_AUX_OP_FULL_RESOLVE) {
iris_emit_pipe_control_flush(batch,
"hiz op: post-flush",
PIPE_CONTROL_DATA_CACHE_FLUSH |
PIPE_CONTROL_CS_STALL);
}
iris_batch_sync_region_end(batch);
}