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i965: Define and use REG_MASK macro to make masked MMIO writes slightly more readable.

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Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg  <krh@bitplanet.net>
This commit is contained in:
Francisco Jerez 2015-11-26 16:42:43 +02:00
parent fa043698d2
commit 353abb294b
4 changed files with 9 additions and 3 deletions
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6
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -41,6 +41,12 @@
#define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
#define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
/**
* For use with masked MMIO registers where the upper 16 bits control which
* of the lower bits are committed to the register.
*/
#define REG_MASK(value) ((value) << 16)
#ifndef BRW_DEFINES_H
#define BRW_DEFINES_H

2
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -387,7 +387,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_CACHE_MODE_1);
OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) |
OUT_BATCH(REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
ADVANCE_BATCH();
}

2
src/mesa/drivers/dri/i965/gen7_l3_state.c
View file

@ -268,7 +268,7 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
OUT_BATCH(HSW_SCRATCH1);
OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE);
OUT_BATCH(HSW_ROW_CHICKEN3);
OUT_BATCH(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE << 16 |
OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) |
(has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE));
ADVANCE_BATCH();
}

2
src/mesa/drivers/dri/i965/intel_reg.h
View file

@ -183,7 +183,7 @@
# define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
# define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
# define GEN8_HIZ_PMA_MASK_BITS \
((GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) << 16)
REG_MASK(GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE)
/* Predicate registers */
#define MI_PREDICATE_SRC0 0x2400