From 351b8c6aec55b5ec79057ff1f7fa02b796d768f1 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 8 Feb 2021 16:45:08 -0800 Subject: [PATCH] intel/fs: Enable nir_op_imul_32x16 and nir_op_umul_32x16 on pre-Gfx7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Even though Intel's CI doesn't test these old platforms anymore, the validation added in "intel/eu/validate: Validate integer multiplication source size restrictions" combined with full shader-db runs gives me confidence in the changes. Sandy Bridge total instructions in shared programs: 13902341 -> 13902167 (<.01%) instructions in affected programs: 30771 -> 30597 (-0.57%) helped: 66 / HURT: 0 total cycles in shared programs: 741795500 -> 741791931 (<.01%) cycles in affected programs: 987602 -> 984033 (-0.36%) helped: 28 / HURT: 5 Iron Lake total instructions in shared programs: 8365806 -> 8365754 (<.01%) instructions in affected programs: 1766 -> 1714 (-2.94%) helped: 10 / HURT: 0 total cycles in shared programs: 248542694 -> 248542378 (<.01%) cycles in affected programs: 29836 -> 29520 (-1.06%) helped: 9 / HURT: 0 GM45 total instructions in shared programs: 5187127 -> 5187101 (<.01%) instructions in affected programs: 891 -> 865 (-2.92%) helped: 5 / HURT: 0 total cycles in shared programs: 163643914 -> 163643750 (<.01%) cycles in affected programs: 22206 -> 22042 (-0.74%) helped: 5 / HURT: 0 Reviewed-by: Marcin Ślusarz Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 13 ++++++------- src/intel/compiler/brw_nir.c | 2 +- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index c85983f1c4f..c5ee5baad97 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1323,17 +1323,16 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, assert(nir_dest_bit_size(instr->dest.dest) == 32); - /* Before Gfx7, the order of the 32-bit source and the 16-bit source was - * swapped. The extension isn't enabled on those platforms, so don't - * pretend to support the differences. - */ - assert(devinfo->ver >= 7); - /* Before copy propagation there are no immediate values. */ assert(op[0].file != IMM && op[1].file != IMM); op[1] = subscript(op[1], word_type, 0); - bld.MUL(result, retype(op[0], dword_type), op[1]); + + if (devinfo->ver >= 7) + bld.MUL(result, retype(op[0], dword_type), op[1]); + else + bld.MUL(result, op[1], retype(op[0], dword_type)); + break; } diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index b9d46d0065b..fcea4b40b54 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1286,7 +1286,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, OPT(brw_nir_opt_peephole_ffma); } - if (devinfo->ver >= 7 && is_scalar) + if (is_scalar) OPT(brw_nir_opt_peephole_imul32x16); if (OPT(nir_opt_comparison_pre)) {