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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-09 11:08:03 +02:00
gallivm: Switch to reg intrinsics
This is pretty straightforward, since we don't try to "coalesce" register access the way a GPU backend would. In the old path, we generated register load/store instructions internally when hitting register sources/destinations. In the new path, we just translate the register load/store intrinsics to the LLVM loads/stores and we're back where we started. It's a bit more code, but it's more straightforward. Notably, although this continues to use registers, this does NOT use the chasing helpers. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
fded7e7b66
commit
35030fc79c
4 changed files with 141 additions and 115 deletions
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@ -36,6 +36,7 @@
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#include "lp_bld_struct.h"
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#include "lp_bld_debug.h"
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#include "lp_bld_printf.h"
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#include "nir.h"
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#include "nir_deref.h"
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#include "nir_search_helpers.h"
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@ -150,36 +151,10 @@ glsl_sampler_to_pipe(int sampler_dim, bool is_array)
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}
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static LLVMValueRef get_ssa_src(struct lp_build_nir_context *bld_base, nir_ssa_def *ssa)
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{
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return bld_base->ssa_defs[ssa->index];
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}
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static LLVMValueRef
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get_src(struct lp_build_nir_context *bld_base, nir_src src);
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static LLVMValueRef
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get_reg_src(struct lp_build_nir_context *bld_base, nir_register_src src)
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{
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struct hash_entry *entry = _mesa_hash_table_search(bld_base->regs, src.reg);
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LLVMValueRef reg_storage = (LLVMValueRef)entry->data;
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struct lp_build_context *reg_bld = get_int_bld(bld_base, true, src.reg->bit_size);
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LLVMValueRef indir_src = NULL;
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if (src.indirect)
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indir_src = get_src(bld_base, *src.indirect);
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return bld_base->load_reg(bld_base, reg_bld, &src, indir_src, reg_storage);
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}
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static LLVMValueRef
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get_src(struct lp_build_nir_context *bld_base, nir_src src)
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{
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if (src.is_ssa)
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return get_ssa_src(bld_base, src.ssa);
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else
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return get_reg_src(bld_base, src.reg);
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return bld_base->ssa_defs[src.ssa->index];
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}
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@ -204,46 +179,6 @@ assign_ssa_dest(struct lp_build_nir_context *bld_base, const nir_ssa_def *ssa,
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}
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static void
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assign_reg(struct lp_build_nir_context *bld_base, const nir_register_dest *reg,
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unsigned write_mask,
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LLVMValueRef vals[NIR_MAX_VEC_COMPONENTS])
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{
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assert(write_mask != 0x0);
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struct hash_entry *entry = _mesa_hash_table_search(bld_base->regs, reg->reg);
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LLVMValueRef reg_storage = (LLVMValueRef)entry->data;
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struct lp_build_context *reg_bld = get_int_bld(bld_base, true, reg->reg->bit_size);
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LLVMValueRef indir_src = NULL;
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if (reg->indirect)
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indir_src = get_src(bld_base, *reg->indirect);
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bld_base->store_reg(bld_base, reg_bld, reg, write_mask,
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indir_src, reg_storage, vals);
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}
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static void
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assign_dest(struct lp_build_nir_context *bld_base,
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const nir_dest *dest,
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LLVMValueRef vals[NIR_MAX_VEC_COMPONENTS])
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{
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if (dest->is_ssa)
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assign_ssa_dest(bld_base, &dest->ssa, vals);
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else
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assign_reg(bld_base, &dest->reg, 0xf, vals);
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}
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static void
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assign_alu_dest(struct lp_build_nir_context *bld_base,
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const nir_alu_dest *dest,
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LLVMValueRef vals[NIR_MAX_VEC_COMPONENTS])
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{
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if (dest->dest.is_ssa)
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assign_ssa_dest(bld_base, &dest->dest.ssa, vals);
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else
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assign_reg(bld_base, &dest->dest.reg, dest->write_mask, vals);
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}
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static LLVMValueRef
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fcmp32(struct lp_build_nir_context *bld_base,
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enum pipe_compare_func compare,
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@ -1218,17 +1153,6 @@ visit_alu(struct lp_build_nir_context *bld_base,
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src_bit_size[i] = nir_src_bit_size(instr->src[i].src);
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}
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if (instr->op == nir_op_mov &&
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is_aos(bld_base) &&
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!instr->dest.dest.is_ssa) {
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for (unsigned i = 0; i < 4; i++) {
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if (instr->dest.write_mask & (1 << i)) {
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assign_reg(bld_base, &instr->dest.dest.reg, (1 << i), src);
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}
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}
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return;
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}
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LLVMValueRef result[NIR_MAX_VEC_COMPONENTS];
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if (instr->op == nir_op_vec4 ||
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instr->op == nir_op_vec3 ||
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@ -1278,7 +1202,7 @@ visit_alu(struct lp_build_nir_context *bld_base,
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nir_dest_bit_size(instr->dest.dest));
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}
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}
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assign_alu_dest(bld_base, &instr->dest, result);
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assign_ssa_dest(bld_base, &instr->dest.dest.ssa, result);
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}
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@ -1416,6 +1340,79 @@ visit_store_output(struct lp_build_nir_context *bld_base,
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bit_size, &var, mask, NULL, 0, indir_index, src);
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}
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static void
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visit_load_reg(struct lp_build_nir_context *bld_base,
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nir_intrinsic_instr *instr,
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LLVMValueRef result[NIR_MAX_VEC_COMPONENTS])
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{
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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LLVMBuilderRef builder = gallivm->builder;
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nir_intrinsic_instr *decl = nir_reg_get_decl(instr->src[0].ssa);
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unsigned base = nir_intrinsic_base(instr);
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struct hash_entry *entry = _mesa_hash_table_search(bld_base->regs, decl);
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LLVMValueRef reg_storage = (LLVMValueRef)entry->data;
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unsigned bit_size = nir_intrinsic_bit_size(decl);
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struct lp_build_context *reg_bld = get_int_bld(bld_base, true, bit_size);
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LLVMValueRef indir_src = NULL;
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if (instr->intrinsic == nir_intrinsic_load_reg_indirect) {
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indir_src = cast_type(bld_base, get_src(bld_base, instr->src[1]),
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nir_type_uint, 32);
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}
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LLVMValueRef val = bld_base->load_reg(bld_base, reg_bld, decl, base, indir_src, reg_storage);
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if (!is_aos(bld_base) && nir_dest_num_components(instr->dest) > 1) {
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for (unsigned i = 0; i < nir_dest_num_components(instr->dest); i++)
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result[i] = LLVMBuildExtractValue(builder, val, i, "");
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} else {
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result[0] = val;
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}
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}
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static void
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visit_store_reg(struct lp_build_nir_context *bld_base,
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nir_intrinsic_instr *instr)
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{
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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LLVMBuilderRef builder = gallivm->builder;
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nir_intrinsic_instr *decl = nir_reg_get_decl(instr->src[1].ssa);
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unsigned base = nir_intrinsic_base(instr);
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unsigned write_mask = nir_intrinsic_write_mask(instr);
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assert(write_mask != 0x0);
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LLVMValueRef val = get_src(bld_base, instr->src[0]);
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LLVMValueRef vals[NIR_MAX_VEC_COMPONENTS] = { NULL };
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if (!is_aos(bld_base) && nir_src_num_components(instr->src[0]) > 1) {
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for (unsigned i = 0; i < nir_src_num_components(instr->src[0]); i++)
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vals[i] = LLVMBuildExtractValue(builder, val, i, "");
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} else {
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vals[0] = val;
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}
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struct hash_entry *entry = _mesa_hash_table_search(bld_base->regs, decl);
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LLVMValueRef reg_storage = (LLVMValueRef)entry->data;
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unsigned bit_size = nir_intrinsic_bit_size(decl);
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struct lp_build_context *reg_bld = get_int_bld(bld_base, true, bit_size);
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LLVMValueRef indir_src = NULL;
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if (instr->intrinsic == nir_intrinsic_store_reg_indirect) {
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indir_src = cast_type(bld_base, get_src(bld_base, instr->src[2]),
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nir_type_uint, 32);
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}
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bld_base->store_reg(bld_base, reg_bld, decl, write_mask, base,
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indir_src, reg_storage, vals);
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}
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static bool
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compact_array_index_oob(struct lp_build_nir_context *bld_base, nir_variable *var, const uint32_t index)
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{
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@ -2137,6 +2134,17 @@ visit_intrinsic(struct lp_build_nir_context *bld_base,
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{
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LLVMValueRef result[NIR_MAX_VEC_COMPONENTS] = {0};
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switch (instr->intrinsic) {
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case nir_intrinsic_decl_reg:
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/* already handled */
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break;
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case nir_intrinsic_load_reg:
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case nir_intrinsic_load_reg_indirect:
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visit_load_reg(bld_base, instr, result);
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break;
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case nir_intrinsic_store_reg:
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case nir_intrinsic_store_reg_indirect:
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visit_store_reg(bld_base, instr);
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break;
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case nir_intrinsic_load_input:
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visit_load_input(bld_base, instr, result);
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break;
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@ -2333,7 +2341,8 @@ visit_intrinsic(struct lp_build_nir_context *bld_base,
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break;
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}
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if (result[0]) {
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assign_dest(bld_base, &instr->dest, result);
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assert(instr->dest.is_ssa);
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assign_ssa_dest(bld_base, &instr->dest.ssa, result);
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}
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}
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@ -2379,8 +2388,9 @@ visit_txs(struct lp_build_nir_context *bld_base, nir_tex_instr *instr)
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params.resource = resource;
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bld_base->tex_size(bld_base, ¶ms);
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assign_dest(bld_base, &instr->dest,
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&sizes_out[instr->op == nir_texop_query_levels ? 3 : 0]);
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assert(instr->dest.is_ssa);
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assign_ssa_dest(bld_base, &instr->dest.ssa,
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&sizes_out[instr->op == nir_texop_query_levels ? 3 : 0]);
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}
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@ -2686,7 +2696,8 @@ visit_tex(struct lp_build_nir_context *bld_base, nir_tex_instr *instr)
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}
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}
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assign_dest(bld_base, &instr->dest, texel);
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assert(instr->dest.is_ssa);
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assign_ssa_dest(bld_base, &instr->dest.ssa, texel);
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}
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@ -2855,19 +2866,23 @@ handle_shader_output_decl(struct lp_build_nir_context *bld_base,
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*/
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static LLVMTypeRef
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get_register_type(struct lp_build_nir_context *bld_base,
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nir_register *reg)
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nir_intrinsic_instr *reg)
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{
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if (is_aos(bld_base))
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return bld_base->base.int_vec_type;
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unsigned num_array_elems = nir_intrinsic_num_array_elems(reg);
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unsigned bit_size = nir_intrinsic_bit_size(reg);
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unsigned num_components = nir_intrinsic_num_components(reg);
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struct lp_build_context *int_bld =
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get_int_bld(bld_base, true, reg->bit_size == 1 ? 32 : reg->bit_size);
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get_int_bld(bld_base, true, bit_size == 1 ? 32 : bit_size);
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LLVMTypeRef type = int_bld->vec_type;
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if (reg->num_components > 1)
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type = LLVMArrayType(type, reg->num_components);
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if (reg->num_array_elems)
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type = LLVMArrayType(type, reg->num_array_elems);
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if (num_components > 1)
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type = LLVMArrayType(type, num_components);
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if (num_array_elems)
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type = LLVMArrayType(type, num_array_elems);
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return type;
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}
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@ -2878,14 +2893,14 @@ bool lp_build_nir_llvm(struct lp_build_nir_context *bld_base,
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{
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struct nir_function *func;
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NIR_PASS_V(nir, nir_convert_from_ssa, true, false);
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NIR_PASS_V(nir, nir_lower_locals_to_regs, 32);
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NIR_PASS_V(nir, nir_convert_from_ssa, true, true);
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NIR_PASS_V(nir, nir_lower_locals_to_reg_intrinsics, 32);
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NIR_PASS_V(nir, nir_remove_dead_derefs);
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NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
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if (is_aos(bld_base)) {
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NIR_PASS_V(nir, nir_move_vec_src_uses_to_dest);
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NIR_PASS_V(nir, nir_lower_vec_to_movs, NULL, NULL);
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NIR_PASS_V(nir, nir_lower_vec_to_regs, NULL, NULL);
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}
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nir_foreach_shader_out_variable(variable, nir)
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@ -2915,7 +2930,7 @@ bool lp_build_nir_llvm(struct lp_build_nir_context *bld_base,
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func = (struct nir_function *)exec_list_get_head(&nir->functions);
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nir_foreach_register(reg, &func->impl->registers) {
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nir_foreach_reg_decl(reg, func->impl) {
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LLVMTypeRef type = get_register_type(bld_base, reg);
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LLVMValueRef reg_alloc = lp_build_alloca(bld_base->base.gallivm,
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type, "reg");
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@ -161,13 +161,15 @@ struct lp_build_nir_context
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LLVMValueRef (*load_reg)(struct lp_build_nir_context *bld_base,
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struct lp_build_context *reg_bld,
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const nir_register_src *reg,
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const nir_intrinsic_instr *decl,
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unsigned base,
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LLVMValueRef indir_src,
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LLVMValueRef reg_storage);
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void (*store_reg)(struct lp_build_nir_context *bld_base,
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struct lp_build_context *reg_bld,
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const nir_register_dest *reg,
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const nir_intrinsic_instr *decl,
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unsigned writemask,
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unsigned base,
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LLVMValueRef indir_src,
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LLVMValueRef reg_storage,
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LLVMValueRef dst[NIR_MAX_VEC_COMPONENTS]);
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@ -162,11 +162,13 @@ emit_store_var(struct lp_build_nir_context *bld_base,
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static LLVMValueRef
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emit_load_reg(struct lp_build_nir_context *bld_base,
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struct lp_build_context *reg_bld,
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const nir_register_src *reg,
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const nir_intrinsic_instr *decl,
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unsigned base,
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LLVMValueRef indir_src,
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LLVMValueRef reg_storage)
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{
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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assert(indir_src == NULL && "no indirects with linear path");
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return LLVMBuildLoad2(gallivm->builder, reg_bld->vec_type, reg_storage, "");
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}
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@ -205,14 +207,16 @@ swizzle_writemask(struct lp_build_nir_aos_context *bld,
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static void
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emit_store_reg(struct lp_build_nir_context *bld_base,
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struct lp_build_context *reg_bld,
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const nir_register_dest *reg,
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const nir_intrinsic_instr *decl,
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unsigned writemask,
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unsigned base,
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LLVMValueRef indir_src,
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LLVMValueRef reg_storage,
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LLVMValueRef vals[NIR_MAX_VEC_COMPONENTS])
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{
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struct lp_build_nir_aos_context *bld = lp_nir_aos_context(bld_base);
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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assert(indir_src == NULL && "no indirects with linear path");
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if (writemask == 0xf) {
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LLVMBuildStore(gallivm->builder, vals[0], reg_storage);
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@ -827,19 +827,20 @@ static void emit_store_var(struct lp_build_nir_context *bld_base,
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*/
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static LLVMValueRef reg_chan_pointer(struct lp_build_nir_context *bld_base,
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struct lp_build_context *reg_bld,
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const nir_register *reg,
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const nir_intrinsic_instr *decl,
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LLVMValueRef reg_storage,
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int array_index, int chan)
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{
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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int nc = reg->num_components;
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int nc = nir_intrinsic_num_components(decl);
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int num_array_elems = nir_intrinsic_num_array_elems(decl);
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LLVMTypeRef chan_type = reg_bld->vec_type;
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if (nc > 1)
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chan_type = LLVMArrayType(chan_type, nc);
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if (reg->num_array_elems > 0) {
|
||||
LLVMTypeRef array_type = LLVMArrayType(chan_type, reg->num_array_elems);
|
||||
if (num_array_elems > 0) {
|
||||
LLVMTypeRef array_type = LLVMArrayType(chan_type, num_array_elems);
|
||||
reg_storage = lp_build_array_get_ptr2(gallivm, array_type, reg_storage,
|
||||
lp_build_const_int32(gallivm, array_index));
|
||||
}
|
||||
|
|
@ -853,18 +854,20 @@ static LLVMValueRef reg_chan_pointer(struct lp_build_nir_context *bld_base,
|
|||
|
||||
static LLVMValueRef emit_load_reg(struct lp_build_nir_context *bld_base,
|
||||
struct lp_build_context *reg_bld,
|
||||
const nir_register_src *reg,
|
||||
const nir_intrinsic_instr *decl,
|
||||
unsigned base,
|
||||
LLVMValueRef indir_src,
|
||||
LLVMValueRef reg_storage)
|
||||
{
|
||||
struct gallivm_state *gallivm = bld_base->base.gallivm;
|
||||
LLVMBuilderRef builder = gallivm->builder;
|
||||
int nc = reg->reg->num_components;
|
||||
int nc = nir_intrinsic_num_components(decl);
|
||||
int num_array_elems = nir_intrinsic_num_array_elems(decl);
|
||||
LLVMValueRef vals[NIR_MAX_VEC_COMPONENTS] = { NULL };
|
||||
struct lp_build_context *uint_bld = &bld_base->uint_bld;
|
||||
if (reg->indirect) {
|
||||
LLVMValueRef indirect_val = lp_build_const_int_vec(gallivm, uint_bld->type, reg->base_offset);
|
||||
LLVMValueRef max_index = lp_build_const_int_vec(gallivm, uint_bld->type, reg->reg->num_array_elems - 1);
|
||||
if (indir_src != NULL) {
|
||||
LLVMValueRef indirect_val = lp_build_const_int_vec(gallivm, uint_bld->type, base);
|
||||
LLVMValueRef max_index = lp_build_const_int_vec(gallivm, uint_bld->type, num_array_elems - 1);
|
||||
indirect_val = LLVMBuildAdd(builder, indirect_val, indir_src, "");
|
||||
indirect_val = lp_build_min(uint_bld, indirect_val, max_index);
|
||||
reg_storage = LLVMBuildBitCast(builder, reg_storage, LLVMPointerType(reg_bld->elem_type, 0), "");
|
||||
|
|
@ -875,8 +878,8 @@ static LLVMValueRef emit_load_reg(struct lp_build_nir_context *bld_base,
|
|||
} else {
|
||||
for (unsigned i = 0; i < nc; i++) {
|
||||
vals[i] = LLVMBuildLoad2(builder, reg_bld->vec_type,
|
||||
reg_chan_pointer(bld_base, reg_bld, reg->reg, reg_storage,
|
||||
reg->base_offset, i), "");
|
||||
reg_chan_pointer(bld_base, reg_bld, decl, reg_storage,
|
||||
base, i), "");
|
||||
}
|
||||
}
|
||||
return nc == 1 ? vals[0] : lp_nir_array_build_gather_values(builder, vals, nc);
|
||||
|
|
@ -884,8 +887,9 @@ static LLVMValueRef emit_load_reg(struct lp_build_nir_context *bld_base,
|
|||
|
||||
static void emit_store_reg(struct lp_build_nir_context *bld_base,
|
||||
struct lp_build_context *reg_bld,
|
||||
const nir_register_dest *reg,
|
||||
const nir_intrinsic_instr *decl,
|
||||
unsigned writemask,
|
||||
unsigned base,
|
||||
LLVMValueRef indir_src,
|
||||
LLVMValueRef reg_storage,
|
||||
LLVMValueRef dst[NIR_MAX_VEC_COMPONENTS])
|
||||
|
|
@ -894,10 +898,11 @@ static void emit_store_reg(struct lp_build_nir_context *bld_base,
|
|||
struct gallivm_state *gallivm = bld_base->base.gallivm;
|
||||
LLVMBuilderRef builder = gallivm->builder;
|
||||
struct lp_build_context *uint_bld = &bld_base->uint_bld;
|
||||
int nc = reg->reg->num_components;
|
||||
if (reg->indirect) {
|
||||
LLVMValueRef indirect_val = lp_build_const_int_vec(gallivm, uint_bld->type, reg->base_offset);
|
||||
LLVMValueRef max_index = lp_build_const_int_vec(gallivm, uint_bld->type, reg->reg->num_array_elems - 1);
|
||||
int nc = nir_intrinsic_num_components(decl);
|
||||
int num_array_elems = nir_intrinsic_num_array_elems(decl);
|
||||
if (indir_src != NULL) {
|
||||
LLVMValueRef indirect_val = lp_build_const_int_vec(gallivm, uint_bld->type, base);
|
||||
LLVMValueRef max_index = lp_build_const_int_vec(gallivm, uint_bld->type, num_array_elems - 1);
|
||||
indirect_val = LLVMBuildAdd(builder, indirect_val, indir_src, "");
|
||||
indirect_val = lp_build_min(uint_bld, indirect_val, max_index);
|
||||
reg_storage = LLVMBuildBitCast(builder, reg_storage, LLVMPointerType(reg_bld->elem_type, 0), "");
|
||||
|
|
@ -916,8 +921,8 @@ static void emit_store_reg(struct lp_build_nir_context *bld_base,
|
|||
continue;
|
||||
dst[i] = LLVMBuildBitCast(builder, dst[i], reg_bld->vec_type, "");
|
||||
lp_exec_mask_store(&bld->exec_mask, reg_bld, dst[i],
|
||||
reg_chan_pointer(bld_base, reg_bld, reg->reg, reg_storage,
|
||||
reg->base_offset, i));
|
||||
reg_chan_pointer(bld_base, reg_bld, decl, reg_storage,
|
||||
base, i));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue