i965/cs: Enable barrier in MEDIA_INTERFACE_DESCRIPTOR

Enable barrier in MEDIA_INTERFACE_DESCRIPTOR if the program uses the
barrier() GLSL function.

On Ivy Bridge and Haswell, this allows the piglit test
tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test
to pass. On gen8, this enables a similar test with a local group size
of 896 to pass.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
This commit is contained in:
Jordan Justen 2014-11-05 00:47:41 -08:00
parent b01d047391
commit 34cff76fc2
4 changed files with 8 additions and 1 deletions

View file

@ -498,6 +498,7 @@ struct brw_cs_prog_data {
GLuint dispatch_grf_start_reg_16;
unsigned local_size[3];
unsigned simd_size;
bool uses_barrier;
};
/**

View file

@ -431,7 +431,9 @@ brw_upload_cs_state(struct brw_context *brw)
SET_FIELD(threads, GEN8_MEDIA_GPGPU_THREAD_COUNT) :
SET_FIELD(threads, MEDIA_GPGPU_THREAD_COUNT);
assert(threads <= brw->max_cs_threads);
desc[dw++] = media_threads;
desc[dw++] =
SET_FIELD(cs_prog_data->uses_barrier, MEDIA_BARRIER_ENABLE) |
media_threads;
BEGIN_BATCH(4);
OUT_BATCH(MEDIA_INTERFACE_DESCRIPTOR_LOAD << 16 | (4 - 2));

View file

@ -2690,6 +2690,8 @@ enum brw_wm_barycentric_interp_mode {
# define MEDIA_CURBE_READ_OFFSET_SHIFT 0
# define MEDIA_CURBE_READ_OFFSET_MASK INTEL_MASK(15, 0)
/* GEN7 DW5, GEN8+ DW6 */
# define MEDIA_BARRIER_ENABLE_SHIFT 21
# define MEDIA_BARRIER_ENABLE_MASK INTEL_MASK(21, 21)
# define MEDIA_GPGPU_THREAD_COUNT_SHIFT 0
# define MEDIA_GPGPU_THREAD_COUNT_MASK INTEL_MASK(7, 0)
# define GEN8_MEDIA_GPGPU_THREAD_COUNT_SHIFT 0

View file

@ -1705,6 +1705,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
case nir_intrinsic_barrier:
emit_barrier();
if (stage == MESA_SHADER_COMPUTE)
((struct brw_cs_prog_data *) prog_data)->uses_barrier = true;
break;
default: