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nv50-: separate vertex formats from surface format descriptions
We've previously had identical naming between vertex and texture formats, so it mostly made sense to define these together. However, upcoming patches are going to transition the driver over to using updated texture header definitions using NVIDIA's naming, and this will no longer be the case. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ben Skeggs
parent
3e2dd50d81
commit
346d7a24ea
7 changed files with 203 additions and 64 deletions
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@ -39,10 +39,9 @@
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* C: render target (color), blendable only on nvc0
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* D: scanout/display target, blendable
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* Z: depth/stencil
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* V: vertex fetch
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* I: image / surface, implies T
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*/
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#define U_V PIPE_BIND_VERTEX_BUFFER
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#define U_V 0
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#define U_T PIPE_BIND_SAMPLER_VIEW
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#define U_I PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE | PIPE_BIND_COMPUTE_RESOURCE
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#define U_TR PIPE_BIND_RENDER_TARGET | U_T
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@ -103,10 +102,7 @@
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(NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \
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(NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) | \
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(NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) | \
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NV50_TIC_0_FMT_##sz, \
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NVXX_3D_VAF_SIZE(sz) | \
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NVXX_3D_VAF_TYPE(t0) | (br << 31), \
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U_##u \
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NV50_TIC_0_FMT_##sz, U_##u \
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}
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#define TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
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@ -120,7 +116,7 @@
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(NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \
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(NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) | \
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(NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) | \
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NV50_TIC_0_FMT_##sz, 0, U_##u \
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NV50_TIC_0_FMT_##sz, U_##u \
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}
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#define C4A(p, n, r, g, b, a, t, s, u, br) \
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@ -308,6 +304,10 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
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I3B(R32G32B32X32_SINT, RGBX32_SINT, C0, C1, C2, xx, SINT, 32_32_32_32, TR),
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I3B(R32G32B32X32_UINT, RGBX32_UINT, C0, C1, C2, xx, UINT, 32_32_32_32, TR),
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F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
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I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
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I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
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F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
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F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
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F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
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@ -381,64 +381,191 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
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C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 8_8_8_8, T),
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TBLENT_B_(R5SG5SB6U_NORM, 0,
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C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 5_5_6, T),
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};
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/* vertex-only formats: */
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#define V_TBLENT_A_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u, br) \
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[PIPE_FORMAT_##pf] = { \
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NVXX_3D_VAF_SIZE(sz) | NVXX_3D_VAF_TYPE(t0) | (br << 31), \
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PIPE_BIND_VERTEX_BUFFER \
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}
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C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 32_32_32_32, V, 0),
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C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED, 32_32_32_32, V, 0),
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F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
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F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V),
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F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V),
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I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
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I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
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F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 32_32_32, V),
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F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED, 32_32_32, V),
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F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V),
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F2A(R32G32_USCALED, NONE, C0, C1, xx, xx, USCALED, 32_32, V),
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F1A(R32_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 32, V),
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F1A(R32_USCALED, NONE, C0, xx, xx, xx, USCALED, 32, V),
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#define V_TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
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[PIPE_FORMAT_##pf] = { \
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0, \
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PIPE_BIND_VERTEX_BUFFER \
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}
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C4A(R16G16B16A16_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 16_16_16_16, V, 0),
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C4A(R16G16B16A16_USCALED, NONE, C0, C1, C2, C3, USCALED, 16_16_16_16, V, 0),
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F3A(R16G16B16_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 16_16_16, V),
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F3A(R16G16B16_UNORM, NONE, C0, C1, C2, xx, UNORM, 16_16_16, V),
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F3A(R16G16B16_SNORM, NONE, C0, C1, C2, xx, SNORM, 16_16_16, V),
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I3A(R16G16B16_SINT, NONE, C0, C1, C2, xx, SINT, 16_16_16, V),
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I3A(R16G16B16_UINT, NONE, C0, C1, C2, xx, UINT, 16_16_16, V),
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F3A(R16G16B16_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 16_16_16, V),
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F3A(R16G16B16_USCALED, NONE, C0, C1, C2, xx, USCALED, 16_16_16, V),
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F2A(R16G16_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 16_16, V),
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F2A(R16G16_USCALED, NONE, C0, C1, xx, xx, USCALED, 16_16, V),
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F1A(R16_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 16, V),
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F1A(R16_USCALED, NONE, C0, xx, xx, xx, USCALED, 16, V),
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#define V_C4A(p, n, r, g, b, a, t, s, u, br) \
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V_TBLENT_A_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u, br)
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#define V_C4B(p, n, r, g, b, a, t, s, u) \
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V_TBLENT_B_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u)
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C4A(R10G10B10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 0),
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C4A(R10G10B10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 0),
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C4A(B10G10R10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 1),
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C4A(B10G10R10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 1),
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#define V_ZXB(p, n, r, g, b, a, t, s, u) \
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V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
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r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
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#define V_ZSB(p, n, r, g, b, a, t, s, u) \
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V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
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r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
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#define V_SZB(p, n, r, g, b, a, t, s, u) \
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V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
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r, g, b, ONE_FLOAT, UINT, t, UINT, UINT, s, u)
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#define V_SXB(p, r, s, u) \
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V_TBLENT_B_(p, NV50_ZETA_FORMAT_NONE, \
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r, r, r, r, UINT, UINT, UINT, UINT, s, u)
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C4A(R8G8B8A8_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 8_8_8_8, V, 0),
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C4A(R8G8B8A8_USCALED, NONE, C0, C1, C2, C3, USCALED, 8_8_8_8, V, 0),
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F3A(R8G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, 8_8_8, V),
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F3A(R8G8B8_SNORM, NONE, C0, C1, C2, xx, SNORM, 8_8_8, V),
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I2A(R8G8B8_SINT, NONE, C0, C1, C2, xx, SINT, 8_8_8, V),
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I2A(R8G8B8_UINT, NONE, C0, C1, C2, xx, UINT, 8_8_8, V),
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F3A(R8G8B8_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 8_8_8, V),
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F3A(R8G8B8_USCALED, NONE, C0, C1, C2, xx, USCALED, 8_8_8, V),
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F2A(R8G8_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 8_8, V),
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F2A(R8G8_USCALED, NONE, C0, C1, xx, xx, USCALED, 8_8, V),
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F1A(R8_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 8, V),
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F1A(R8_USCALED, NONE, C0, xx, xx, xx, USCALED, 8, V),
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#define V_F3A(p, n, r, g, b, a, t, s, u) \
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V_C4A(p, n, r, g, b, ONE_FLOAT, t, s, u, 0)
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#define V_I3A(p, n, r, g, b, a, t, s, u) \
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V_C4A(p, n, r, g, b, ONE_INT, t, s, u, 0)
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#define V_F3B(p, n, r, g, b, a, t, s, u) \
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V_C4B(p, n, r, g, b, ONE_FLOAT, t, s, u)
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#define V_I3B(p, n, r, g, b, a, t, s, u) \
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V_C4B(p, n, r, g, b, ONE_INT, t, s, u)
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#define V_F2A(p, n, r, g, b, a, t, s, u) \
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V_C4A(p, n, r, g, ZERO, ONE_FLOAT, t, s, u, 0)
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#define V_I2A(p, n, r, g, b, a, t, s, u) \
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V_C4A(p, n, r, g, ZERO, ONE_INT, t, s, u, 0)
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#define V_F2B(p, n, r, g, b, a, t, s, u) \
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V_C4B(p, n, r, g, ZERO, ONE_FLOAT, t, s, u)
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#define V_I2B(p, n, r, g, b, a, t, s, u) \
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V_C4B(p, n, r, g, ZERO, ONE_INT, t, s, u)
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#define V_F1A(p, n, r, g, b, a, t, s, u) \
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V_C4A(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u, 0)
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#define V_I1A(p, n, r, g, b, a, t, s, u) \
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V_C4A(p, n, r, ZERO, ZERO, ONE_INT, t, s, u, 0)
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#define V_F1B(p, n, r, g, b, a, t, s, u) \
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V_C4B(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u)
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#define V_I1B(p, n, r, g, b, a, t, s, u) \
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V_C4B(p, n, r, ZERO, ZERO, ONE_INT, t, s, u)
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#define V_A1B(p, n, r, g, b, a, t, s, u) \
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V_C4B(p, n, ZERO, ZERO, ZERO, a, t, s, u)
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#if NOUVEAU_DRIVER == 0xc0
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const struct nvc0_vertex_format nvc0_vertex_format[PIPE_FORMAT_COUNT] =
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#else
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const struct nv50_vertex_format nv50_vertex_format[PIPE_FORMAT_COUNT] =
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#endif
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{
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V_C4A(B8G8R8A8_UNORM, BGRA8_UNORM, C2, C1, C0, C3, UNORM, 8_8_8_8, TDV, 1),
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V_C4A(R8G8B8A8_UNORM, RGBA8_UNORM, C0, C1, C2, C3, UNORM, 8_8_8_8, IBV, 0),
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V_C4A(R10G10B10A2_UNORM, RGB10_A2_UNORM, C0, C1, C2, C3, UNORM, 10_10_10_2, IBV, 0),
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V_C4A(B10G10R10A2_UNORM, BGR10_A2_UNORM, C2, C1, C0, C3, UNORM, 10_10_10_2, TDV, 1),
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V_C4A(R10G10B10A2_SNORM, NONE, C0, C1, C2, C3, SNORM, 10_10_10_2, TV, 0),
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V_C4A(B10G10R10A2_SNORM, NONE, C2, C1, C0, C3, SNORM, 10_10_10_2, TV, 1),
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V_C4A(R10G10B10A2_UINT, RGB10_A2_UINT, C0, C1, C2, C3, UINT, 10_10_10_2, TRV, 0),
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V_C4A(B10G10R10A2_UINT, RGB10_A2_UINT, C2, C1, C0, C3, UINT, 10_10_10_2, TV, 0),
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V_F3A(R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT, 11_11_10, IBV),
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V_C4A(R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT, 32_32_32_32, IBV, 0),
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V_C4A(R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32, TV, 0),
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V_C4A(R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM, 32_32_32_32, TV, 0),
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V_C4A(R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT, 32_32_32_32, IRV, 0),
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V_C4A(R32G32B32A32_UINT, RGBA32_UINT, C0, C1, C2, C3, UINT, 32_32_32_32, IRV, 0),
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V_F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
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V_F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
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V_F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
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V_I2A(R32G32_SINT, RG32_SINT, C0, C1, xx, xx, SINT, 32_32, IRV),
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V_I2A(R32G32_UINT, RG32_UINT, C0, C1, xx, xx, UINT, 32_32, IRV),
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V_F1A(R32_FLOAT, R32_FLOAT, C0, xx, xx, xx, FLOAT, 32, IBV),
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V_F1A(R32_UNORM, NONE, C0, xx, xx, xx, UNORM, 32, TV),
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V_F1A(R32_SNORM, NONE, C0, xx, xx, xx, SNORM, 32, TV),
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V_I1A(R32_SINT, R32_SINT, C0, xx, xx, xx, SINT, 32, IRV),
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V_I1A(R32_UINT, R32_UINT, C0, xx, xx, xx, UINT, 32, IRV),
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V_C4A(R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT, 16_16_16_16, IBV, 0),
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V_C4A(R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM, 16_16_16_16, ICV, 0),
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V_C4A(R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM, 16_16_16_16, ICV, 0),
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V_C4A(R16G16B16A16_SINT, RGBA16_SINT, C0, C1, C2, C3, SINT, 16_16_16_16, IRV, 0),
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V_C4A(R16G16B16A16_UINT, RGBA16_UINT, C0, C1, C2, C3, UINT, 16_16_16_16, IRV, 0),
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V_F2A(R16G16_FLOAT, RG16_FLOAT, C0, C1, xx, xx, FLOAT, 16_16, IBV),
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V_F2A(R16G16_UNORM, RG16_UNORM, C0, C1, xx, xx, UNORM, 16_16, ICV),
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V_F2A(R16G16_SNORM, RG16_SNORM, C0, C1, xx, xx, SNORM, 16_16, ICV),
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V_I2A(R16G16_SINT, RG16_SINT, C0, C1, xx, xx, SINT, 16_16, IRV),
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V_I2A(R16G16_UINT, RG16_UINT, C0, C1, xx, xx, UINT, 16_16, IRV),
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V_F1A(R16_FLOAT, R16_FLOAT, C0, xx, xx, xx, FLOAT, 16, IBV),
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V_F1A(R16_UNORM, R16_UNORM, C0, xx, xx, xx, UNORM, 16, ICV),
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V_F1A(R16_SNORM, R16_SNORM, C0, xx, xx, xx, SNORM, 16, ICV),
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V_I1A(R16_SINT, R16_SINT, C0, xx, xx, xx, SINT, 16, IRV),
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V_I1A(R16_UINT, R16_UINT, C0, xx, xx, xx, UINT, 16, IRV),
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V_C4A(R8G8B8A8_SNORM, RGBA8_SNORM, C0, C1, C2, C3, SNORM, 8_8_8_8, ICV, 0),
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V_C4A(R8G8B8A8_SINT, RGBA8_SINT, C0, C1, C2, C3, SINT, 8_8_8_8, IRV, 0),
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V_C4A(R8G8B8A8_UINT, RGBA8_UINT, C0, C1, C2, C3, UINT, 8_8_8_8, IRV, 0),
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V_F2A(R8G8_UNORM, RG8_UNORM, C0, C1, xx, xx, UNORM, 8_8, IBV),
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V_F2A(R8G8_SNORM, RG8_SNORM, C0, C1, xx, xx, SNORM, 8_8, ICV),
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V_I2A(R8G8_SINT, RG8_SINT, C0, C1, xx, xx, SINT, 8_8, IRV),
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V_I2A(R8G8_UINT, RG8_UINT, C0, C1, xx, xx, UINT, 8_8, IRV),
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|
||||
V_F1A(R8_UNORM, R8_UNORM, C0, xx, xx, xx, UNORM, 8, IBV),
|
||||
V_F1A(R8_SNORM, R8_SNORM, C0, xx, xx, xx, SNORM, 8, ICV),
|
||||
V_I1A(R8_SINT, R8_SINT, C0, xx, xx, xx, SINT, 8, IRV),
|
||||
V_I1A(R8_UINT, R8_UINT, C0, xx, xx, xx, UINT, 8, IRV),
|
||||
|
||||
V_C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 32_32_32_32, V, 0),
|
||||
V_C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED, 32_32_32_32, V, 0),
|
||||
V_F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
|
||||
V_F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V),
|
||||
V_F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V),
|
||||
V_I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
|
||||
V_I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
|
||||
V_F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 32_32_32, V),
|
||||
V_F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED, 32_32_32, V),
|
||||
V_F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V),
|
||||
V_F2A(R32G32_USCALED, NONE, C0, C1, xx, xx, USCALED, 32_32, V),
|
||||
V_F1A(R32_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 32, V),
|
||||
V_F1A(R32_USCALED, NONE, C0, xx, xx, xx, USCALED, 32, V),
|
||||
|
||||
V_C4A(R16G16B16A16_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 16_16_16_16, V, 0),
|
||||
V_C4A(R16G16B16A16_USCALED, NONE, C0, C1, C2, C3, USCALED, 16_16_16_16, V, 0),
|
||||
V_F3A(R16G16B16_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 16_16_16, V),
|
||||
V_F3A(R16G16B16_UNORM, NONE, C0, C1, C2, xx, UNORM, 16_16_16, V),
|
||||
V_F3A(R16G16B16_SNORM, NONE, C0, C1, C2, xx, SNORM, 16_16_16, V),
|
||||
V_I3A(R16G16B16_SINT, NONE, C0, C1, C2, xx, SINT, 16_16_16, V),
|
||||
V_I3A(R16G16B16_UINT, NONE, C0, C1, C2, xx, UINT, 16_16_16, V),
|
||||
V_F3A(R16G16B16_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 16_16_16, V),
|
||||
V_F3A(R16G16B16_USCALED, NONE, C0, C1, C2, xx, USCALED, 16_16_16, V),
|
||||
V_F2A(R16G16_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 16_16, V),
|
||||
V_F2A(R16G16_USCALED, NONE, C0, C1, xx, xx, USCALED, 16_16, V),
|
||||
V_F1A(R16_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 16, V),
|
||||
V_F1A(R16_USCALED, NONE, C0, xx, xx, xx, USCALED, 16, V),
|
||||
|
||||
V_C4A(R10G10B10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 0),
|
||||
V_C4A(R10G10B10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 0),
|
||||
V_C4A(B10G10R10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 1),
|
||||
V_C4A(B10G10R10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 1),
|
||||
|
||||
V_C4A(R8G8B8A8_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 8_8_8_8, V, 0),
|
||||
V_C4A(R8G8B8A8_USCALED, NONE, C0, C1, C2, C3, USCALED, 8_8_8_8, V, 0),
|
||||
V_F3A(R8G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, 8_8_8, V),
|
||||
V_F3A(R8G8B8_SNORM, NONE, C0, C1, C2, xx, SNORM, 8_8_8, V),
|
||||
V_I2A(R8G8B8_SINT, NONE, C0, C1, C2, xx, SINT, 8_8_8, V),
|
||||
V_I2A(R8G8B8_UINT, NONE, C0, C1, C2, xx, UINT, 8_8_8, V),
|
||||
V_F3A(R8G8B8_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 8_8_8, V),
|
||||
V_F3A(R8G8B8_USCALED, NONE, C0, C1, C2, xx, USCALED, 8_8_8, V),
|
||||
V_F2A(R8G8_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 8_8, V),
|
||||
V_F2A(R8G8_USCALED, NONE, C0, C1, xx, xx, USCALED, 8_8, V),
|
||||
V_F1A(R8_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 8, V),
|
||||
V_F1A(R8_USCALED, NONE, C0, xx, xx, xx, USCALED, 8, V),
|
||||
|
||||
/* FIXED types: not supported natively, converted on VBO push */
|
||||
|
||||
C4B(R32G32B32A32_FIXED, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
|
||||
F3B(R32G32B32_FIXED, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
|
||||
F2B(R32G32_FIXED, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
|
||||
F1B(R32_FIXED, NONE, C0, xx, xx, xx, FLOAT, 32, V),
|
||||
V_C4B(R32G32B32A32_FIXED, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
|
||||
V_F3B(R32G32B32_FIXED, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
|
||||
V_F2B(R32G32_FIXED, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
|
||||
V_F1B(R32_FIXED, NONE, C0, xx, xx, xx, FLOAT, 32, V),
|
||||
|
||||
C4B(R64G64B64A64_FLOAT, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
|
||||
F3B(R64G64B64_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
|
||||
F2B(R64G64_FLOAT, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
|
||||
F1B(R64_FLOAT, NONE, C0, xx, xx, xx, FLOAT, 32, V),
|
||||
V_C4B(R64G64B64A64_FLOAT, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
|
||||
V_F3B(R64G64B64_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
|
||||
V_F2B(R64G64_FLOAT, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
|
||||
V_F1B(R64_FLOAT, NONE, C0, xx, xx, xx, FLOAT, 32, V),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -72,7 +72,8 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen,
|
|||
PIPE_BIND_TRANSFER_WRITE |
|
||||
PIPE_BIND_SHARED);
|
||||
|
||||
return (nv50_format_table[format].usage & bindings) == bindings;
|
||||
return (( nv50_format_table[format].usage |
|
||||
nv50_vertex_format[format].usage) & bindings) == bindings;
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
|
|||
|
|
@ -157,11 +157,16 @@ nv50_resource_validate(struct nv04_resource *res, uint32_t flags)
|
|||
struct nv50_format {
|
||||
uint32_t rt;
|
||||
uint32_t tic;
|
||||
uint32_t usage;
|
||||
};
|
||||
|
||||
struct nv50_vertex_format {
|
||||
uint32_t vtx;
|
||||
uint32_t usage;
|
||||
};
|
||||
|
||||
extern const struct nv50_format nv50_format_table[];
|
||||
extern const struct nv50_vertex_format nv50_vertex_format[];
|
||||
|
||||
static inline void
|
||||
nv50_screen_tic_unlock(struct nv50_screen *screen, struct nv50_tic_entry *tic)
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ nv50_vertex_state_create(struct pipe_context *pipe,
|
|||
enum pipe_format fmt = ve->src_format;
|
||||
|
||||
so->element[i].pipe = elements[i];
|
||||
so->element[i].state = nv50_format_table[fmt].vtx;
|
||||
so->element[i].state = nv50_vertex_format[fmt].vtx;
|
||||
|
||||
if (!so->element[i].state) {
|
||||
switch (util_format_get_nr_components(fmt)) {
|
||||
|
|
@ -89,7 +89,7 @@ nv50_vertex_state_create(struct pipe_context *pipe,
|
|||
FREE(so);
|
||||
return NULL;
|
||||
}
|
||||
so->element[i].state = nv50_format_table[fmt].vtx;
|
||||
so->element[i].state = nv50_vertex_format[fmt].vtx;
|
||||
so->need_conversion = true;
|
||||
pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
|
||||
"Converting vertex element %d, no hw format %s",
|
||||
|
|
|
|||
|
|
@ -61,7 +61,8 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
|
|||
PIPE_BIND_TRANSFER_WRITE |
|
||||
PIPE_BIND_SHARED);
|
||||
|
||||
return (nvc0_format_table[format].usage & bindings) == bindings;
|
||||
return (( nvc0_format_table[format].usage |
|
||||
nvc0_vertex_format[format].usage) & bindings) == bindings;
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
|
|||
|
|
@ -165,11 +165,16 @@ nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)
|
|||
struct nvc0_format {
|
||||
uint32_t rt;
|
||||
uint32_t tic;
|
||||
uint32_t usage;
|
||||
};
|
||||
|
||||
struct nvc0_vertex_format {
|
||||
uint32_t vtx;
|
||||
uint32_t usage;
|
||||
};
|
||||
|
||||
extern const struct nvc0_format nvc0_format_table[];
|
||||
extern const struct nvc0_vertex_format nvc0_vertex_format[];
|
||||
|
||||
static inline void
|
||||
nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe,
|
|||
enum pipe_format fmt = ve->src_format;
|
||||
|
||||
so->element[i].pipe = elements[i];
|
||||
so->element[i].state = nvc0_format_table[fmt].vtx;
|
||||
so->element[i].state = nvc0_vertex_format[fmt].vtx;
|
||||
|
||||
if (!so->element[i].state) {
|
||||
switch (util_format_get_nr_components(fmt)) {
|
||||
|
|
@ -93,7 +93,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe,
|
|||
FREE(so);
|
||||
return NULL;
|
||||
}
|
||||
so->element[i].state = nvc0_format_table[fmt].vtx;
|
||||
so->element[i].state = nvc0_vertex_format[fmt].vtx;
|
||||
so->need_conversion = true;
|
||||
pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
|
||||
"Converting vertex element %d, no hw format %s",
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue