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st/mesa: remove random L3 pinning heuristic for glthread

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This is not very effective. A better solution will be added to glthread.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7054>
This commit is contained in:
Marek Olšák 2020-10-06 21:37:01 -04:00 • committed by Marge Bot
parent 96d9f7761d
commit 3433d193e7
3 changed files with 0 additions and 62 deletions
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47
src/gallium/auxiliary/util/u_helpers.c
View file

@ -157,53 +157,6 @@ util_upload_index_buffer(struct pipe_context *pipe,
return *out_buffer != NULL;
}
/**
* Called by MakeCurrent. Used to notify the driver that the application
* thread may have been changed.
*
* The function pins the current thread and driver threads to a group of
* CPU cores that share the same L3 cache. This is needed for good multi-
* threading performance on AMD Zen CPUs.
*
* \param upper_thread thread in gallium frontends that also needs to be
* pinned.
*/
void
util_pin_driver_threads_to_random_L3(struct pipe_context *ctx,
thrd_t *upper_thread)
{
/* If pinning has no effect, don't do anything. */
if (util_cpu_caps.nr_cpus == util_cpu_caps.cores_per_L3)
return;
unsigned num_L3_caches = util_cpu_caps.nr_cpus /
util_cpu_caps.cores_per_L3;
/* Get a semi-random number. */
int64_t t = os_time_get_nano();
unsigned cache = (t ^ (t >> 8) ^ (t >> 16)) % num_L3_caches;
/* Tell the driver to pin its threads to the selected L3 cache. */
if (ctx->set_context_param) {
ctx->set_context_param(ctx, PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
cache);
}
/* Do the same for the upper level thread if there is any (e.g. glthread) */
if (upper_thread)
util_pin_thread_to_L3(*upper_thread, cache, util_cpu_caps.cores_per_L3);
/* Optionally pin the application thread to the same L3 to get maximum
* performance with glthread on AMD Zen. (this function is only called
* with glthread) This is used to estimate and remove the overhead of
* Infinity Fabric between L3 caches.
*/
#if defined(HAVE_PTHREAD)
if (debug_get_bool_option("pin_app_thread", false))
util_pin_thread_to_L3(pthread_self(), cache, util_cpu_caps.cores_per_L3);
#endif
}
/* This is a helper for hardware bring-up. Don't remove. */
struct pipe_query *
util_begin_pipestat_query(struct pipe_context *ctx)

4
src/gallium/auxiliary/util/u_helpers.h
View file

@ -75,10 +75,6 @@ util_varying_is_point_coord(gl_varying_slot slot, uint32_t sprite_coord_enable)
return false;
}
void
util_pin_driver_threads_to_random_L3(struct pipe_context *ctx,
thrd_t *upper_thread);
struct pipe_query *
util_begin_pipestat_query(struct pipe_context *ctx);

11
src/mesa/state_tracker/st_manager.c
View file

@ -821,17 +821,6 @@ st_start_thread(struct st_context_iface *stctxi)
struct st_context *st = (struct st_context *) stctxi;
_mesa_glthread_init(st->ctx);
/* Pin all driver threads to one L3 cache for optimal performance
* on AMD Zen. This is only done if glthread is enabled.
*
* If glthread is disabled, st_draw.c re-pins driver threads regularly
* based on the location of the app thread.
*/
struct glthread_state *glthread = &st->ctx->GLThread;
if (glthread->enabled && st->pipe->set_context_param) {
util_pin_driver_threads_to_random_L3(st->pipe, &glthread->queue.threads[0]);
}
}