diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 9f736a66541..b291ef77483 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1807,12 +1807,14 @@ fs_nir_emit_load_const(nir_to_brw_state &ntb,
                        nir_load_const_instr *instr)
 {
    const intel_device_info *devinfo = ntb.devinfo;
-   const fs_builder &bld = ntb.bld;
+   const fs_builder &bld = ntb.bld.scalar_group();
 
    const brw_reg_type reg_type =
       brw_type_with_size(BRW_TYPE_D, instr->def.bit_size);
    brw_reg reg = bld.vgrf(reg_type, instr->def.num_components);
 
+   reg.is_scalar = true;
+
    brw_reg comps[NIR_MAX_VEC_COMPONENTS];
 
    switch (instr->def.bit_size) {
@@ -4814,11 +4816,7 @@ try_rebuild_source(nir_to_brw_state &ntb, const brw::fs_builder &bld,
       nir_instr *instr = def->parent_instr;
       switch (instr->type) {
       case nir_instr_type_load_const: {
-         nir_load_const_instr *load_const =
-            nir_instr_as_load_const(instr);
-         ubld.MOV(brw_imm_d(load_const->value[0].i32),
-                  &ntb.resource_insts[def->index]);
-         break;
+         unreachable("load_const should already be is_scalar");
       }
 
       case nir_instr_type_alu: {