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ac: add radeon_info::tcc_harvested

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Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 8cbe83445b)
Conflicts resolved by Dylan Baker

Conflicts:
	src/amd/common/ac_gpu_info.h
This commit is contained in:
Marek Olšák 2019-09-24 16:56:21 -04:00 • committed by Dylan Baker
parent 2bbe4c69c8
commit 33eecbcc9b
2 changed files with 5 additions and 0 deletions
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4
src/amd/common/ac_gpu_info.c
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@ -427,6 +427,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
}
if (info->chip_class >= GFX10) {
info->tcc_cache_line_size = 128;
/* This is a hack, but it's all we can do without a kernel upgrade. */
info->tcc_harvested =
(info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
} else {
info->tcc_cache_line_size = 64;
}
@ -548,6 +551,7 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
printf(" tcc_harvested = %u\n", info->tcc_harvested);
printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);

1
src/amd/common/ac_gpu_info.h
View file

@ -58,6 +58,7 @@ struct radeon_info {
uint32_t num_sdma_rings;
uint32_t clock_crystal_freq;
uint32_t tcc_cache_line_size;
bool tcc_harvested;
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */