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brw: Remove the extra function call when lowering samplers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36730>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
71c23c6722
commit
339a4e8680
1 changed files with 82 additions and 111 deletions
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@ -770,29 +770,92 @@ shader_opcode_uses_sampler(opcode op)
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}
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}
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static void
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lower_sampler_logical_send(const brw_builder &bld, brw_inst *inst,
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const brw_reg &coordinate,
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const brw_reg &shadow_c,
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brw_reg lod, const brw_reg &lod2,
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const brw_reg &min_lod,
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const brw_reg &sample_index,
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const brw_reg &mcs,
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const brw_reg &surface,
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const brw_reg &sampler,
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const brw_reg &surface_handle,
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const brw_reg &sampler_handle,
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const brw_reg &tg4_offset,
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unsigned payload_type_bit_size,
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unsigned coord_components,
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unsigned grad_components,
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bool residency)
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static unsigned
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get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo,
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const brw_inst *inst)
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{
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assert(inst);
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const brw_reg *src = inst->src;
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unsigned src_type_size = 0;
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/* All sources need to have the same size, therefore seek the first valid
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* and take the size from there.
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*/
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for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) {
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if (src[i].file != BAD_FILE) {
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src_type_size = brw_type_size_bytes(src[i].type);
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break;
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}
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}
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assert(src_type_size == 2 || src_type_size == 4);
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#ifndef NDEBUG
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/* Make sure all sources agree. On gfx12 this doesn't hold when sampling
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* compressed multisampled surfaces. There the payload contains MCS data
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* which is already in 16-bits unlike the other parameters that need forced
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* conversion.
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*/
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if (inst->opcode != SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) {
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for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) {
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assert(src[i].file == BAD_FILE ||
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brw_type_size_bytes(src[i].type) == src_type_size);
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}
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}
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#endif
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if (devinfo->verx10 < 125)
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return src_type_size * 8;
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/* Force conversion from 32-bit sources to 16-bit payload. From the XeHP Bspec:
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* 3D and GPGPU Programs - Shared Functions - 3D Sampler - Messages - Message
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* Format [GFX12:HAS:1209977870] *
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*
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* ld2dms_w SIMD8H and SIMD16H Only
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* ld_mcs SIMD8H and SIMD16H Only
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* ld2dms REMOVEDBY(GEN:HAS:1406788836)
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*/
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if (inst->opcode == SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL ||
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inst->opcode == SHADER_OPCODE_TXF_MCS_LOGICAL)
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src_type_size = 2;
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return src_type_size * 8;
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}
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static void
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lower_sampler_logical_send(const brw_builder &bld, brw_inst *inst)
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{
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const intel_device_info *devinfo = bld.shader->devinfo;
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const brw_compiler *compiler = bld.shader->compiler;
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const brw_reg coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE];
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const brw_reg shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C];
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const brw_reg lod = inst->src[TEX_LOGICAL_SRC_LOD];
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const brw_reg lod2 = inst->src[TEX_LOGICAL_SRC_LOD2];
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const brw_reg min_lod = inst->src[TEX_LOGICAL_SRC_MIN_LOD];
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const brw_reg sample_index = inst->src[TEX_LOGICAL_SRC_SAMPLE_INDEX];
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const brw_reg mcs = inst->src[TEX_LOGICAL_SRC_MCS];
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const brw_reg surface = inst->src[TEX_LOGICAL_SRC_SURFACE];
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const brw_reg sampler = inst->src[TEX_LOGICAL_SRC_SAMPLER];
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const brw_reg surface_handle = inst->src[TEX_LOGICAL_SRC_SURFACE_HANDLE];
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const brw_reg sampler_handle = inst->src[TEX_LOGICAL_SRC_SAMPLER_HANDLE];
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const brw_reg tg4_offset = inst->src[TEX_LOGICAL_SRC_TG4_OFFSET];
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assert(inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM);
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const unsigned coord_components = inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud;
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assert(inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM);
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const unsigned grad_components = inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud;
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assert(inst->src[TEX_LOGICAL_SRC_RESIDENCY].file == IMM);
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const bool residency = inst->src[TEX_LOGICAL_SRC_RESIDENCY].ud != 0;
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const unsigned payload_type_bit_size =
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get_sampler_msg_payload_type_bit_size(devinfo, inst);
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/* 16-bit payloads are available only on gfx11+ */
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assert(payload_type_bit_size != 16 || devinfo->ver >= 11);
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/* We never generate EOT sampler messages */
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assert(!inst->eot);
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const brw_compiler *compiler = bld.shader->compiler;
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const intel_device_info *devinfo = bld.shader->devinfo;
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const enum brw_reg_type payload_type =
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brw_type_with_size(BRW_TYPE_F, payload_type_bit_size);
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const enum brw_reg_type payload_unsigned_type =
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@ -1245,98 +1308,6 @@ lower_sampler_logical_send(const brw_builder &bld, brw_inst *inst,
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assert(inst->mlen <= MAX_SAMPLER_MESSAGE_SIZE * reg_unit(devinfo));
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}
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static unsigned
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get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo,
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const brw_inst *inst)
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{
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assert(inst);
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const brw_reg *src = inst->src;
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unsigned src_type_size = 0;
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/* All sources need to have the same size, therefore seek the first valid
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* and take the size from there.
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*/
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for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) {
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if (src[i].file != BAD_FILE) {
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src_type_size = brw_type_size_bytes(src[i].type);
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break;
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}
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}
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assert(src_type_size == 2 || src_type_size == 4);
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#ifndef NDEBUG
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/* Make sure all sources agree. On gfx12 this doesn't hold when sampling
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* compressed multisampled surfaces. There the payload contains MCS data
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* which is already in 16-bits unlike the other parameters that need forced
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* conversion.
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*/
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if (inst->opcode != SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) {
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for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) {
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assert(src[i].file == BAD_FILE ||
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brw_type_size_bytes(src[i].type) == src_type_size);
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}
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}
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#endif
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if (devinfo->verx10 < 125)
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return src_type_size * 8;
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/* Force conversion from 32-bit sources to 16-bit payload. From the XeHP Bspec:
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* 3D and GPGPU Programs - Shared Functions - 3D Sampler - Messages - Message
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* Format [GFX12:HAS:1209977870] *
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*
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* ld2dms_w SIMD8H and SIMD16H Only
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* ld_mcs SIMD8H and SIMD16H Only
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* ld2dms REMOVEDBY(GEN:HAS:1406788836)
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*/
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if (inst->opcode == SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL ||
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inst->opcode == SHADER_OPCODE_TXF_MCS_LOGICAL)
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src_type_size = 2;
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return src_type_size * 8;
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}
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static void
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lower_sampler_logical_send(const brw_builder &bld, brw_inst *inst)
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{
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const intel_device_info *devinfo = bld.shader->devinfo;
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const brw_reg coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE];
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const brw_reg shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C];
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const brw_reg lod = inst->src[TEX_LOGICAL_SRC_LOD];
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const brw_reg lod2 = inst->src[TEX_LOGICAL_SRC_LOD2];
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const brw_reg min_lod = inst->src[TEX_LOGICAL_SRC_MIN_LOD];
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const brw_reg sample_index = inst->src[TEX_LOGICAL_SRC_SAMPLE_INDEX];
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const brw_reg mcs = inst->src[TEX_LOGICAL_SRC_MCS];
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const brw_reg surface = inst->src[TEX_LOGICAL_SRC_SURFACE];
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const brw_reg sampler = inst->src[TEX_LOGICAL_SRC_SAMPLER];
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const brw_reg surface_handle = inst->src[TEX_LOGICAL_SRC_SURFACE_HANDLE];
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const brw_reg sampler_handle = inst->src[TEX_LOGICAL_SRC_SAMPLER_HANDLE];
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const brw_reg tg4_offset = inst->src[TEX_LOGICAL_SRC_TG4_OFFSET];
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assert(inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM);
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const unsigned coord_components = inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud;
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assert(inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM);
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const unsigned grad_components = inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud;
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assert(inst->src[TEX_LOGICAL_SRC_RESIDENCY].file == IMM);
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const bool residency = inst->src[TEX_LOGICAL_SRC_RESIDENCY].ud != 0;
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const unsigned msg_payload_type_bit_size =
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get_sampler_msg_payload_type_bit_size(devinfo, inst);
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/* 16-bit payloads are available only on gfx11+ */
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assert(msg_payload_type_bit_size != 16 || devinfo->ver >= 11);
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lower_sampler_logical_send(bld, inst, coordinate,
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shadow_c, lod, lod2, min_lod,
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sample_index,
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mcs, surface, sampler,
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surface_handle, sampler_handle,
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tg4_offset,
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msg_payload_type_bit_size,
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coord_components, grad_components,
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residency);
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}
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/**
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* Predicate the specified instruction on the vector mask.
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*/
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