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i965: take ownership rather than adding reference for new renderbuffers

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This avoids locking in the reference calls and fixes a leak after the
RefCount initialisation was change from 0 to 1.

Fixes: 32141e53d1 (mesa: tidy up renderbuffer RefCount initialisation)

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This commit is contained in:
Timothy Arceri 2017-04-08 10:22:16 +10:00
parent c355675440
commit 3387f66cab
1 changed files with 7 additions and 6 deletions
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13
src/mesa/drivers/dri/i965/intel_screen.c
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@ -1158,11 +1158,11 @@ intelCreateBuffer(__DRIscreen *dri_screen,
/* setup the hardware-based renderbuffers */ /* setup the hardware-based renderbuffers */
rb = intel_create_renderbuffer(rgbFormat, num_samples); rb = intel_create_renderbuffer(rgbFormat, num_samples);
_mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &rb->Base.Base); _mesa_add_renderbuffer_without_ref(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
if (mesaVis->doubleBufferMode) { if (mesaVis->doubleBufferMode) {
rb = intel_create_renderbuffer(rgbFormat, num_samples); rb = intel_create_renderbuffer(rgbFormat, num_samples);
_mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &rb->Base.Base); _mesa_add_renderbuffer_without_ref(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
} }
/* /*
@ -1176,10 +1176,11 @@ intelCreateBuffer(__DRIscreen *dri_screen,
if (screen->devinfo.has_hiz_and_separate_stencil) { if (screen->devinfo.has_hiz_and_separate_stencil) {
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT, rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT,
num_samples); num_samples);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base); _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
rb = intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8, rb = intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8,
num_samples); num_samples);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base); _mesa_add_renderbuffer_without_ref(fb, BUFFER_STENCIL,
&rb->Base.Base);
} else { } else {
/* /*
* Use combined depth/stencil. Note that the renderbuffer is * Use combined depth/stencil. Note that the renderbuffer is
@ -1187,7 +1188,7 @@ intelCreateBuffer(__DRIscreen *dri_screen,
*/ */
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT, rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT,
num_samples); num_samples);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base); _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base); _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
} }
} }
@ -1195,7 +1196,7 @@ intelCreateBuffer(__DRIscreen *dri_screen,
assert(mesaVis->stencilBits == 0); assert(mesaVis->stencilBits == 0);
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16, rb = intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16,
num_samples); num_samples);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base); _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
} }
else { else {
assert(mesaVis->depthBits == 0); assert(mesaVis->depthBits == 0);