From 338273dedde33acfc636c21086e612ea9b30184e Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 19 Jun 2023 16:37:46 -0700 Subject: [PATCH] brw/reg_allocate: Optimize spill offset calculation using integer MAD Gfx12.5 and later allow the use of two 16-bit immediate values in integer MAD. Gfx11 and Gfx12 allow a single immediate for integer MAD, but that is not helpful where. v2: brw_reg_alloc::build_lane_offsets is only used on Gfx12.5+, so the check around using integer MAD is unnecessary. No shader-db or fossil-db changes on any pre-Gfx12.5 platforms. shader-db: Lunar Lake, Meteor Lake, and DG2 had similar results. (Lunar Lake shown) total instructions in shared programs: 17119962 -> 17118441 (<.01%) instructions in affected programs: 65398 -> 63877 (-2.33%) helped: 32 / HURT: 0 total cycles in shared programs: 895433316 -> 895425578 (<.01%) cycles in affected programs: 13437376 -> 13429638 (-0.06%) helped: 30 / HURT: 2 fossil-db: Lunar Lake, Meteor Lake, and DG2 had similar results. (Lunar Lake shown) Totals: Instrs: 210052706 -> 209550074 (-0.24%) Cycle count: 31486266412 -> 31436238696 (-0.16%); split: -0.16%, +0.00% Totals from 7081 (1.00% of 707082) affected shaders: Instrs: 16864614 -> 16361982 (-2.98%) Cycle count: 6323185782 -> 6273158066 (-0.79%); split: -0.79%, +0.00% Reviewed-by: Matt Turner Part-of: --- src/intel/compiler/brw_reg_allocate.cpp | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/src/intel/compiler/brw_reg_allocate.cpp b/src/intel/compiler/brw_reg_allocate.cpp index 64ef671aaa4..cc1cdd4f401 100644 --- a/src/intel/compiler/brw_reg_allocate.cpp +++ b/src/intel/compiler/brw_reg_allocate.cpp @@ -737,14 +737,22 @@ brw_reg_alloc::build_lane_offsets(const brw_builder &bld, uint32_t spill_offset, brw_imm_uv(0x76543210)); _mesa_set_add(spill_insts, inst); - /* Make the offset a dword */ - inst = ubld.group(8, 0).SHL(offset, retype(offset, BRW_TYPE_UW), brw_imm_uw(2)); - _mesa_set_add(spill_insts, inst); - - /* Add the base offset */ - if (spill_offset) { - inst = ubld.group(8, 0).ADD(offset, offset, brw_imm_ud(spill_offset)); + if (spill_offset > 0 && spill_offset <= 0xffffu) { + inst = ubld.MAD(offset, + brw_imm_uw(spill_offset), + retype(offset, BRW_TYPE_UW), + brw_imm_uw(4)); _mesa_set_add(spill_insts, inst); + } else { + /* Make the offset a dword */ + inst = ubld.group(8, 0).SHL(offset, retype(offset, BRW_TYPE_UW), brw_imm_uw(2)); + _mesa_set_add(spill_insts, inst); + + /* Add the base offset */ + if (spill_offset) { + inst = ubld.group(8, 0).ADD(offset, offset, brw_imm_ud(spill_offset)); + _mesa_set_add(spill_insts, inst); + } } /* Build offsets in the upper 8 lanes of SIMD16 */