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intel/common: Ensure SIMD16 for fast-clear kernel (xe2)

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Add a restriction on SIMD mode for fast-clear pixel
shader according to the Bspec.

Backport-to: 24.2
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29907>
(cherry picked from commit cb7f816fc4)
This commit is contained in:
Jianxun Zhang 2024-06-25 22:44:43 -07:00 • committed by Eric Engestrom
parent 1112f171d7
commit 33700e5b2b
2 changed files with 23 additions and 13 deletions
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2
.pick_status.json
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@ -514,7 +514,7 @@
"description": "intel/common: Ensure SIMD16 for fast-clear kernel (xe2)",
"nominated": true,
"nomination_type": 4,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

34
src/intel/common/intel_genX_state_brw.h
View file

@ -51,8 +51,22 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
bool enable_8 = prog_data->dispatch_8;
bool enable_16 = prog_data->dispatch_16;
bool enable_32 = prog_data->dispatch_32;
uint8_t dispatch_multi = prog_data->dispatch_multi;
#if GFX_VER >= 9 && GFX_VER < 20
#if GFX_VER >= 20
if (ps->RenderTargetFastClearEnable) {
/* Bspec 57340 (r59562):
*
* Clearing shader must use SIMD16 dispatch mode.
*
* The spec doesn't state if a fast-clear shader can be multi-poly. We
* just assume it can't.
*/
assert(enable_16);
enable_32 = enable_8 = false;
dispatch_multi = 0;
}
#elif GFX_VER >= 9
/* SKL PRMs, Volume 2a: Command Reference: Instructions:
* 3DSTATE_PS_BODY::8 Pixel Dispatch Enable:
*
@ -118,19 +132,16 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
}
assert(enable_8 || enable_16 || enable_32 ||
(GFX_VER >= 12 && prog_data->dispatch_multi));
assert(!prog_data->dispatch_multi ||
(GFX_VER >= 12 && !enable_8));
(GFX_VER >= 12 && dispatch_multi));
assert(!dispatch_multi || (GFX_VER >= 12 && !enable_8));
#if GFX_VER >= 20
if (prog_data->dispatch_multi) {
if (dispatch_multi) {
ps->Kernel0Enable = true;
ps->Kernel0SIMDWidth = (prog_data->dispatch_multi == 32 ?
PS_SIMD32 : PS_SIMD16);
ps->Kernel0SIMDWidth = (dispatch_multi == 32 ? PS_SIMD32 : PS_SIMD16);
ps->Kernel0MaximumPolysperThread =
prog_data->max_polygons - 1;
switch (prog_data->dispatch_multi /
prog_data->max_polygons) {
switch (dispatch_multi / prog_data->max_polygons) {
case 8:
ps->Kernel0PolyPackingPolicy = POLY_PACK8_FIXED;
break;
@ -151,13 +162,12 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
ps->Kernel1Enable = true;
ps->Kernel1SIMDWidth = PS_SIMD32;
} else if (enable_16 && prog_data->dispatch_multi == 16) {
} else if (enable_16 && dispatch_multi == 16) {
ps->Kernel1Enable = true;
ps->Kernel1SIMDWidth = PS_SIMD16;
}
#else
ps->_8PixelDispatchEnable = enable_8 ||
(GFX_VER == 12 && prog_data->dispatch_multi);
ps->_8PixelDispatchEnable = enable_8 || (GFX_VER == 12 && dispatch_multi);
ps->_16PixelDispatchEnable = enable_16;
ps->_32PixelDispatchEnable = enable_32;
#endif