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radv, aco: Don't lower 16bit isign.

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Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17440>
This commit is contained in:
Georg Lehmann 2022-07-09 14:04:16 +02:00 • committed by Marge Bot
parent 4be6164ac9
commit 333f056edf
2 changed files with 7 additions and 1 deletions
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6
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -1546,6 +1546,12 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
} else if (dst.regClass() == v1) {
bld.vop3(aco_opcode::v_med3_i32, Definition(dst), Operand::c32(-1), src, Operand::c32(1u));
} else if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX9) {
bld.vop3(aco_opcode::v_med3_i16, Definition(dst), Operand::c16(-1), src, Operand::c16(1u));
} else if (dst.regClass() == v2b) {
src = as_vgpr(ctx, src);
bld.vop2(aco_opcode::v_max_i16, Definition(dst), Operand::c16(-1),
bld.vop2(aco_opcode::v_min_i16, Definition(bld.tmp(v1)), Operand::c16(1u), src));
} else if (dst.regClass() == v2) {
Temp upper = emit_extract_vector(ctx, src, 1, v1);
Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand::c32(31u), upper);

2
src/amd/vulkan/radv_pipeline.c
View file

@ -3950,7 +3950,6 @@ lower_bit_size_callback(const nir_instr *instr, void *_)
case nir_op_bitfield_select:
case nir_op_imul_high:
case nir_op_umul_high:
case nir_op_isign:
return 32;
case nir_op_iabs:
case nir_op_imax:
@ -3960,6 +3959,7 @@ lower_bit_size_callback(const nir_instr *instr, void *_)
case nir_op_ishr:
case nir_op_ushr:
case nir_op_ishl:
case nir_op_isign:
case nir_op_uadd_sat:
case nir_op_usub_sat:
return (bit_size == 8 || !(chip >= GFX8 && nir_dest_is_divergent(alu->dest.dest))) ? 32