From 33342848451ca06deb054fad94de3cea3a9efe63 Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Mon, 8 Sep 2025 21:54:34 -0700 Subject: [PATCH] brw: Don't set destination of branch instructions In Gfx9+ the destination should be set to ARF null in all those cases, the use of IP was a requirement of old versions only. The already zeroed bits will encode ARF null, so no need to set. Skipping the helper avoids setting unwanted bits (like hstride), which in Gfx12+ are MBZ. This patch adjust the expectations of the asm tests to remove the dst type and dst stride fields -- will expect them all zeroed. Reviewed-by: Sagar Ghuge Part-of: --- src/intel/compiler/brw/brw_eu_emit.c | 10 ---------- src/intel/compiler/brw/brw_gram.y | 11 ----------- src/intel/compiler/brw/tests/gen9/break.expected | 8 ++++---- src/intel/compiler/brw/tests/gen9/cont.expected | 4 ++-- src/intel/compiler/brw/tests/gen9/else.expected | 6 +++--- src/intel/compiler/brw/tests/gen9/halt.expected | 8 ++++---- src/intel/compiler/brw/tests/gen9/if.expected | 10 +++++----- src/intel/compiler/brw/tests/gen9/while.expected | 8 ++++---- 8 files changed, 22 insertions(+), 43 deletions(-) diff --git a/src/intel/compiler/brw/brw_eu_emit.c b/src/intel/compiler/brw/brw_eu_emit.c index 4bedc74f76e..95ddc409b0c 100644 --- a/src/intel/compiler/brw/brw_eu_emit.c +++ b/src/intel/compiler/brw/brw_eu_emit.c @@ -1138,10 +1138,6 @@ brw_IF(struct brw_codegen *p, unsigned execute_size) insn = next_insn(p, BRW_OPCODE_IF); - /* Override the defaults for this instruction: - */ - brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_TYPE_D))); - /* UIP and JIP set by patch_IF_ELSE(). */ brw_eu_inst_set_exec_size(devinfo, insn, execute_size); @@ -1216,8 +1212,6 @@ brw_ELSE(struct brw_codegen *p) insn = next_insn(p, BRW_OPCODE_ELSE); - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_TYPE_D)); - /* UIP and JIP set by patch_IF_ELSE(). */ brw_eu_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); @@ -1282,7 +1276,6 @@ brw_BREAK(struct brw_codegen *p) brw_eu_inst *insn; insn = next_insn(p, BRW_OPCODE_BREAK); - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_TYPE_D)); /* UIP and JIP set by brw_set_uip_jip(). */ @@ -1299,7 +1292,6 @@ brw_CONT(struct brw_codegen *p) brw_eu_inst *insn; insn = next_insn(p, BRW_OPCODE_CONTINUE); - brw_set_dest(p, insn, brw_ip_reg()); /* UIP and JIP set by brw_set_uip_jip(). */ @@ -1315,7 +1307,6 @@ brw_HALT(struct brw_codegen *p) brw_eu_inst *insn; insn = next_insn(p, BRW_OPCODE_HALT); - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_TYPE_D)); /* UIP and JIP set by brw_set_uip_jip(). */ @@ -1353,7 +1344,6 @@ brw_WHILE(struct brw_codegen *p) insn = next_insn(p, BRW_OPCODE_WHILE); do_insn = get_inner_do_insn(p); - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_TYPE_D)); brw_eu_inst_set_jip(devinfo, insn, br * (do_insn - insn)); brw_eu_inst_set_unused_uip(devinfo, insn); diff --git a/src/intel/compiler/brw/brw_gram.y b/src/intel/compiler/brw/brw_gram.y index 4728426c5d2..db8e7db24cd 100644 --- a/src/intel/compiler/brw/brw_gram.y +++ b/src/intel/compiler/brw/brw_gram.y @@ -1129,8 +1129,6 @@ branchinstruction: brw_asm_label_use_uip($6); i965_asm_set_instruction_options(p, $7); brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $2); - - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), BRW_TYPE_D)); } | predicate IF execsize JIP JUMP_LABEL UIP JUMP_LABEL instoptions { @@ -1140,8 +1138,6 @@ branchinstruction: brw_asm_label_use_uip($7); brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, vec1(retype(brw_null_reg(), BRW_TYPE_D))); - brw_pop_insn_state(p); } | predicate GOTO execsize JIP JUMP_LABEL UIP JUMP_LABEL instoptions @@ -1180,8 +1176,6 @@ breakinstruction: i965_asm_set_instruction_options(p, $8); brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), BRW_TYPE_D)); - brw_pop_insn_state(p); } | predicate HALT execsize JIP JUMP_LABEL UIP JUMP_LABEL instoptions @@ -1192,8 +1186,6 @@ breakinstruction: i965_asm_set_instruction_options(p, $8); brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), BRW_TYPE_D)); - brw_pop_insn_state(p); } | predicate CONT execsize JIP JUMP_LABEL UIP JUMP_LABEL instoptions @@ -1203,7 +1195,6 @@ breakinstruction: brw_asm_label_use_uip($7); i965_asm_set_instruction_options(p, $8); brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, brw_ip_reg()); brw_pop_insn_state(p); } @@ -1219,8 +1210,6 @@ loopinstruction: i965_asm_set_instruction_options(p, $6); brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), BRW_TYPE_D)); - brw_pop_insn_state(p); } | DO execsize instoptions diff --git a/src/intel/compiler/brw/tests/gen9/break.expected b/src/intel/compiler/brw/tests/gen9/break.expected index f5448cdbdf3..575e9991167 100644 --- a/src/intel/compiler/brw/tests/gen9/break.expected +++ b/src/intel/compiler/brw/tests/gen9/break.expected @@ -1,4 +1,4 @@ -28 00 60 00 20 0e 00 20 40 00 00 00 20 00 00 00 -28 00 80 00 20 0e 00 20 30 00 00 00 10 00 00 00 -28 00 61 00 20 0e 00 20 20 00 00 00 20 00 00 00 -28 00 81 00 20 0e 00 20 10 00 00 00 10 00 00 00 +28 00 60 00 00 0e 00 00 40 00 00 00 20 00 00 00 +28 00 80 00 00 0e 00 00 30 00 00 00 10 00 00 00 +28 00 61 00 00 0e 00 00 20 00 00 00 20 00 00 00 +28 00 81 00 00 0e 00 00 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/cont.expected b/src/intel/compiler/brw/tests/gen9/cont.expected index d8036df8e1c..2e0fb71b12d 100644 --- a/src/intel/compiler/brw/tests/gen9/cont.expected +++ b/src/intel/compiler/brw/tests/gen9/cont.expected @@ -1,2 +1,2 @@ -29 00 60 00 00 0e 00 34 20 00 00 00 10 00 00 00 -29 00 80 00 00 0e 00 34 10 00 00 00 10 00 00 00 +29 00 60 00 00 0e 00 00 20 00 00 00 10 00 00 00 +29 00 80 00 00 0e 00 00 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/else.expected b/src/intel/compiler/brw/tests/gen9/else.expected index c7834d75bcd..4b322f8926a 100644 --- a/src/intel/compiler/brw/tests/gen9/else.expected +++ b/src/intel/compiler/brw/tests/gen9/else.expected @@ -1,3 +1,3 @@ -24 00 60 00 20 0e 00 20 30 00 00 00 30 00 00 00 -24 00 80 00 20 0e 00 20 20 00 00 00 20 00 00 00 -24 00 a0 00 20 0e 00 20 10 00 00 00 10 00 00 00 +24 00 60 00 00 0e 00 00 30 00 00 00 30 00 00 00 +24 00 80 00 00 0e 00 00 20 00 00 00 20 00 00 00 +24 00 a0 00 00 0e 00 00 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/halt.expected b/src/intel/compiler/brw/tests/gen9/halt.expected index b0867fe7f81..00959ce6163 100644 --- a/src/intel/compiler/brw/tests/gen9/halt.expected +++ b/src/intel/compiler/brw/tests/gen9/halt.expected @@ -1,4 +1,4 @@ -2a 00 76 00 21 0e 00 20 40 00 00 00 40 00 00 00 -2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00 -2a 00 96 00 21 0e 00 20 20 00 00 00 20 00 00 00 -2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00 +2a 00 76 00 01 0e 00 00 40 00 00 00 40 00 00 00 +2a 00 60 00 00 0e 00 00 10 00 00 00 10 00 00 00 +2a 00 96 00 01 0e 00 00 20 00 00 00 20 00 00 00 +2a 00 80 00 00 0e 00 00 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/if.expected b/src/intel/compiler/brw/tests/gen9/if.expected index d11bebc1730..258242a3366 100644 --- a/src/intel/compiler/brw/tests/gen9/if.expected +++ b/src/intel/compiler/brw/tests/gen9/if.expected @@ -1,5 +1,5 @@ -22 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00 -22 00 71 00 20 0e 00 20 40 00 00 00 10 00 00 00 -22 00 91 00 20 0e 00 20 30 00 00 00 30 00 00 00 -22 00 81 00 20 0e 00 20 20 00 00 00 20 00 00 00 -22 00 a1 00 20 0e 00 20 10 00 00 00 10 00 00 00 +22 00 61 00 00 0e 00 00 50 00 00 00 20 00 00 00 +22 00 71 00 00 0e 00 00 40 00 00 00 10 00 00 00 +22 00 91 00 00 0e 00 00 30 00 00 00 30 00 00 00 +22 00 81 00 00 0e 00 00 20 00 00 00 20 00 00 00 +22 00 a1 00 00 0e 00 00 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/while.expected b/src/intel/compiler/brw/tests/gen9/while.expected index 8b6c4da652f..b12b73435b8 100644 --- a/src/intel/compiler/brw/tests/gen9/while.expected +++ b/src/intel/compiler/brw/tests/gen9/while.expected @@ -1,4 +1,4 @@ -27 00 60 00 20 0e 00 20 00 00 00 08 00 00 00 00 -27 00 80 00 20 0e 00 20 00 00 00 08 f0 ff ff ff -27 00 71 00 20 0e 00 20 00 00 00 08 e0 ff ff ff -27 00 91 00 20 0e 00 20 00 00 00 08 d0 ff ff ff +27 00 60 00 00 0e 00 00 00 00 00 08 00 00 00 00 +27 00 80 00 00 0e 00 00 00 00 00 08 f0 ff ff ff +27 00 71 00 00 0e 00 00 00 00 00 08 e0 ff ff ff +27 00 91 00 00 0e 00 00 00 00 00 08 d0 ff ff ff