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intel/isl: Add support for setting component write disables
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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2 changed files with 26 additions and 0 deletions
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@ -589,6 +589,21 @@ typedef uint64_t isl_surf_usage_flags_t;
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#define ISL_SURF_USAGE_CCS_BIT (1u << 15)
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/** @} */
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/**
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* @defgroup Channel Mask
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*
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* These #define values are chosen to match the values of
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* RENDER_SURFACE_STATE::Color Buffer Component Write Disables
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*
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* @{
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*/
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typedef uint8_t isl_channel_mask_t;
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#define ISL_CHANNEL_BLUE_BIT (1 << 0)
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#define ISL_CHANNEL_GREEN_BIT (1 << 1)
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#define ISL_CHANNEL_RED_BIT (1 << 2)
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#define ISL_CHANNEL_ALPHA_BIT (1 << 3)
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/** @} */
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/**
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* @brief A channel select (also known as texture swizzle) value
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*/
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@ -1009,6 +1024,11 @@ struct isl_surf_fill_state_info {
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*/
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union isl_color_value clear_color;
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/**
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* Surface write disables for gen4-5
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*/
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isl_channel_mask_t write_disables;
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/* Intra-tile offset */
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uint16_t x_offset_sa, y_offset_sa;
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};
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@ -256,6 +256,12 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
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s.SurfaceFormat = info->view->format;
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#if GEN_GEN <= 5
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s.ColorBufferComponentWriteDisables = info->write_disables;
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#else
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assert(info->write_disables == 0);
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#endif
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#if GEN_IS_HASWELL
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s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
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#endif
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