From 32c1e45718241f5a768ada47bc1f993a1c3131b5 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 12 Feb 2024 14:05:39 +0100 Subject: [PATCH] radv: fix emitting VS prologs for merged shaders compiled separately on GFX10+ RSRC1 isn't equal to the VS RSRC1 and both config registers need to be re-emitted. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d2ddd87e689..2e3166a2bf0 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3967,7 +3967,7 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v radeon_set_sh_reg(cmd_buffer->cs, pgm_lo_reg, prolog->va >> 8); - if (chip < GFX10) { + if (chip < GFX10 || vs_shader->info.merged_shader_compiled_separately) { radeon_set_sh_reg(cmd_buffer->cs, rsrc1_reg, rsrc1); if (vs_shader->info.merged_shader_compiled_separately) {