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freedreno/a6xx: Fix SP_DS_CTRL_REG0 definition

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Bit 20 isn't actually MERGEDREGS, the mode for the entire geometry
pipeline is controlled by SP_VS_CTRL_REG0::MERGEDREGS and it appears to
be something preamble-related instead since writing any register in the
preamble hangs if it's set. This fixes those hangs on freedreno and
turnip since we no longer set it.

Fixes: fccc35c2de ("ir3: Add preamble optimization pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15801>
This commit is contained in:
Connor Abbott 2022-04-07 19:10:40 +02:00 • committed by Marge Bot
parent 80683943d1
commit 32af90d96f
3 changed files with 8 additions and 5 deletions
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11
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2882,6 +2882,10 @@ to upconvert to 32b float internally?
</bitset>
<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
<!--
This field actually controls all geometry stages. TCS, TES, and
GS must have the same mergedregs setting as VS.
-->
<bitfield name="MERGEDREGS" pos="20" type="boolean"/>
<!-- ??? (blob has it set) -->
<bitfield name="UNK21" pos="21" type="boolean"/>
@ -2998,7 +3002,7 @@ to upconvert to 32b float internally?
<reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
<!--
There is no mergedregs bit, that comes from the previous stage (VS).
There is no mergedregs bit, that comes from the VS.
No idea what this bit does here.
-->
<bitfield name="UNK20" pos="20" type="boolean"/>
@ -3024,7 +3028,8 @@ to upconvert to 32b float internally?
<reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
<reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
<bitfield name="MERGEDREGS" pos="20" type="boolean"/>
<!-- There is no mergedregs bit, that comes from the VS. -->
<bitfield name="UNK20" pos="20" type="boolean"/> <!-- something preamble-related -->
</reg32>
<reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/>
@ -3060,7 +3065,7 @@ to upconvert to 32b float internally?
<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
<!--
There is no mergedregs bit, that comes from the previous stage (VS/DS).
There is no mergedregs bit, that comes from the VS.
No idea what this bit does here.
-->
<bitfield name="UNK20" pos="20" type="boolean"/>

1
src/freedreno/vulkan/tu_pipeline.c
View file

@ -494,7 +494,6 @@ tu6_emit_xs(struct tu_cs *cs,
.fullregfootprint = xs->info.max_reg + 1,
.halfregfootprint = xs->info.max_half_reg + 1,
.branchstack = ir3_shader_branchstack_hw(xs),
.mergedregs = xs->mergedregs,
));
break;
case MESA_SHADER_GEOMETRY:

1
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View file

@ -713,7 +713,6 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
ring,
A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds->info.max_half_reg + 1) |
COND(ds->mergedregs, A6XX_SP_DS_CTRL_REG0_MERGEDREGS) |
A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(ds)));
fd6_emit_shader(ctx, ring, ds);