From 3284f755a3a065764e13b4ad3c43bdfb0f7b0073 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= <daniel@schuermann.dev>
Date: Mon, 22 Mar 2021 19:27:32 +0000
Subject: [PATCH] aco/ra: allow m0 in get_reg_specified()

Totals from 1 (0.00% of 136546) affected shaders (Navi10):
CodeSize: 12788 -> 12776 (-0.09%)
Instrs: 2441 -> 2438 (-0.12%)
Latency: 29713 -> 29731 (+0.06%)
InvThroughput: 14857 -> 14866 (+0.06%)
Copies: 354 -> 353 (-0.28%)
Branches: 66 -> 65 (-1.52%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>
---
 src/amd/compiler/aco_register_allocation.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index 1092615e205..f9bdf636865 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -1204,7 +1204,8 @@ bool get_reg_specified(ra_ctx& ctx,
    PhysRegInterval vcc_win = { vcc, 2 };
    /* VCC is outside the bounds */
    bool is_vcc = rc.type() == RegType::sgpr && vcc_win.contains(reg_win);
-   if (!bounds.contains(reg_win) && !is_vcc)
+   bool is_m0 = rc == s1 && reg == m0;
+   if (!bounds.contains(reg_win) && !is_vcc && !is_m0)
       return false;
 
    if (rc.is_subdword()) {