nouveau: Fix typos.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8490>

src/gallium/drivers/nouveau/codegen/lib/gk104.asm

@@ -563,7 +563,7 @@ gk104_rcp_f64:
    add b32 $r3 $r2 0xffffffff
    joinat #rcp_rejoin
    // We want to check whether the exponent is 0 or 0x7ff (i.e. NaN, inf,
-   // denorm, or 0). Do this by substracting 1 from the exponent, which will
+   // denorm, or 0). Do this by subtracting 1 from the exponent, which will
    // mean that it's > 0x7fd in those cases when doing unsigned comparison
    set $p0 0x1 gt u32 $r3 0x7fd
    // $r3: 0 for norms, 0x36 for denorms, -1 for others
@@ -770,7 +770,7 @@ rsq_norm:
 //
 // Trap handler.
 // Requires at least 4 GPRs and 32 bytes of l[] memory to temporarily save GPRs.
-// Low 32 bytes of l[] memory shouldn't be used if resumeability is required.
+// Low 32 bytes of l[] memory shouldn't be used if resumability is required.
 //
 // Trap info:
 // 0x000: mutex

src/gallium/drivers/nouveau/codegen/lib/gk110.asm

@@ -105,7 +105,7 @@ gk110_rcp_f64:
    add b32 $r3 $r2 0xffffffff
    joinat #rcp_rejoin
    // We want to check whether the exponent is 0 or 0x7ff (i.e. NaN, inf,
-   // denorm, or 0). Do this by substracting 1 from the exponent, which will
+   // denorm, or 0). Do this by subtracting 1 from the exponent, which will
    // mean that it's > 0x7fd in those cases when doing unsigned comparison
    set b32 $p0 0x1 gt u32 $r3 0x7fd
    // $r3: 0 for norms, 0x36 for denorms, -1 for others

src/gallium/drivers/nouveau/codegen/lib/gm107.asm

@@ -119,7 +119,7 @@ gm107_rcp_f64:
    iadd32i $r3 $r2 -1
    ssy #rcp_rejoin
    // We want to check whether the exponent is 0 or 0x7ff (i.e. NaN, inf,
-   // denorm, or 0). Do this by substracting 1 from the exponent, which will
+   // denorm, or 0). Do this by subtracting 1 from the exponent, which will
    // mean that it's > 0x7fd in those cases when doing unsigned comparison
    sched (st 0x0) (st 0x0) (st 0x0)
    isetp gt u32 and $p0 1 $r3 0x7fd 1

src/gallium/drivers/nouveau/codegen/nv50_ir.h

@@ -121,7 +121,7 @@ enum operation
    OP_FINAL, // finish emitting primitives
    OP_TEX,
    OP_TXB, // texture bias
-   OP_TXL, // texure lod
+   OP_TXL, // texture lod
    OP_TXF, // texel fetch
    OP_TXQ, // texture size query
    OP_TXD, // texture derivatives

src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp

@@ -1184,7 +1184,7 @@ bool
 NVC0LoweringPass::handleManualTXD(TexInstruction *i)
 {
    // Always done from the l0 perspective. This is the way that NVIDIA's
-   // driver does it, and doing it from the "current" lane's perpsective
+   // driver does it, and doing it from the "current" lane's perspective
    // doesn't seem to always work for reasons that aren't altogether clear,
    // even in frag shaders.
    //

src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp

@@ -222,7 +222,7 @@ CodeEmitter::prepareEmission(Program *prog)
       func->binPos = prog->binSize;
       prepareEmission(func);
 
-      // adjust sizes & positions for schedulding info:
+      // adjust sizes & positions for scheduling info:
       if (prog->getTarget()->hasSWSched) {
          uint32_t adjPos = func->binPos;
          BasicBlock *bb = NULL;
@@ -390,7 +390,7 @@ Program::emitBinary(struct nv50_ir_prog_info_out *info)
    info->bin.relocData = emit->getRelocInfo();
    info->bin.fixupData = emit->getFixupInfo();
 
-   // the nvc0 driver will print the binary iself together with the header
+   // the nvc0 driver will print the binary itself together with the header
    if ((dbgFlags & NV50_IR_DEBUG_BASIC) && getTarget()->getChipset() < 0xc0)
       emit->printBinary();
 

src/gallium/drivers/nouveau/nv30/nv30_state_validate.c

@@ -80,7 +80,7 @@ nv30_validate_fb(struct nv30_context *nv30)
 
    /* hardware rounds down render target offset to 64 bytes, but surfaces
     * with a size of 2x2 pixel (16bpp) or 1x1 pixel (32bpp) have an
-    * unaligned start aaddress.  For these two important square formats
+    * unaligned start address.  For these two important square formats
     * we can hack around this limitation by adjusting the viewport origin
     */
    if (nv30->state.rt_enable) {

src/gallium/drivers/nouveau/nv50/nv84_video.c

@@ -44,7 +44,7 @@ nv84_copy_firmware(const char *path, void *dest, ssize_t len)
    close(fd);
 
    if (r != len) {
-      fprintf(stderr, "reading firwmare file %s failed: %m\n", path);
+      fprintf(stderr, "reading firmware file %s failed: %m\n", path);
       return 1;
    }
 

src/gallium/drivers/nouveau/nvc0/mme/com9097.mme

@@ -592,7 +592,7 @@ crs_loop:
  * SCRATCH[4] = current counter [low]
  * SCRATCH[5] = current counter [high]
  *
- * arg     = number of parameters to muliply together, ideally 6
+ * arg     = number of parameters to multiply together, ideally 6
  * parm[0] = num_groups_x
  * parm[1] = num_groups_y
  * parm[2] = num_groups_z

src/gallium/drivers/nouveau/nvc0/nvc0_program.c

@@ -361,7 +361,7 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info_out *info
    if (info->target >= NVISA_GM107_CHIPSET) {
       /* On GM107+, the number of output patch components has moved in the TCP
        * header, but it seems like blob still also uses the old position.
-       * Also, the high 8-bits are located inbetween the min/max parallel
+       * Also, the high 8-bits are located in between the min/max parallel
        * field and has to be set after updating the outputs. */
       tcp->hdr[3] = (opcs & 0x0f) << 28;
       tcp->hdr[4] |= (opcs & 0xf0) << 16;

src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c

@@ -149,7 +149,7 @@ nvc0_hw_begin_query(struct nvc0_context *nvc0, struct nvc0_query *q)
       return hq->funcs->begin_query(nvc0, hq);
 
    /* For occlusion queries we have to change the storage, because a previous
-    * query might set the initial render conition to false even *after* we re-
+    * query might set the initial render condition to false even *after* we re-
     * initialized it to true.
     */
    if (hq->rotate) {

src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c

@@ -2436,7 +2436,7 @@ nvc0_hw_sm_begin_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq)
       }
 
       /* Oddly-enough, the signal id depends on the slot selected on Fermi but
-       * not on Kepler. Fortunately, the signal ids are just offseted by the
+       * not on Kepler. Fortunately, the signal ids are just offsetted by the
        * slot id! */
       mask_sel |= c;
       mask_sel |= (c << 8);

src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c

@@ -585,7 +585,7 @@ nvc0_push_vbo(struct nvc0_context *nvc0, const struct pipe_draw_info *info,
       /* NOTE: I hope we won't ever need that last index (~0).
        * If we do, we have to disable primitive restart here always and
        * use END,BEGIN to restart. (XXX: would that affect PrimitiveID ?)
-       * We could also deactive PRIM_RESTART_WITH_DRAW_ARRAYS temporarily,
+       * We could also deactivate PRIM_RESTART_WITH_DRAW_ARRAYS temporarily,
        * and add manual restart to disp_vertices_seq.
        */
       BEGIN_NVC0(ctx.push, NVC0_3D(PRIM_RESTART_ENABLE), 2);