fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-23 19:50:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: Only add END_OF_PIPE_SYNC if we actually have AUX_INVAL

Browse source 
Fixes: 43dc842cb9 "anv: Wait for the GPU to be idle before..."
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
This commit is contained in:
Jason Ekstrand 2020-03-18 13:29:06 -05:00 • committed by Marge Bot
parent 5b57aa79e2
commit 3252041a78
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -2042,7 +2042,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
* add extra flushes in the case it knows that the engine is already * add extra flushes in the case it knows that the engine is already
* IDLE." * IDLE."
*/ */
if (GEN_GEN == 12 && ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) if (GEN_GEN == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT))
bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT; bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
/* If we're going to do an invalidate and we have a pending end-of-pipe /* If we're going to do an invalidate and we have a pending end-of-pipe