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radv/video: support event for pre-VCN4 decode queues

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Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32400>
This commit is contained in:
Benjamin Cheng 2024-10-01 16:09:09 -04:00 • committed by Dave Airlie
parent 1689d88e4a
commit 323b59a5b5
3 changed files with 26 additions and 14 deletions
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19
src/amd/common/ac_vcn_dec.h
View file

@ -73,6 +73,7 @@
#define RDECODE_CMD_BITSTREAM_BUFFER 0x00000100
#define RDECODE_CMD_IT_SCALING_TABLE_BUFFER 0x00000204
#define RDECODE_CMD_CONTEXT_BUFFER 0x00000206
#define RDECODE_CMD_WRITE_MEMORY 0x00000800
#define RDECODE_MSG_CREATE 0x00000000
#define RDECODE_MSG_DECODE 0x00000001
@ -1199,15 +1200,17 @@ struct jpeg_params {
#define RDECODE_VCN1_GPCOM_VCPU_DATA1 0x20714
#define RDECODE_VCN1_ENGINE_CNTL 0x20718
#define RDECODE_VCN2_GPCOM_VCPU_CMD (0x503 << 2)
#define RDECODE_VCN2_GPCOM_VCPU_DATA0 (0x504 << 2)
#define RDECODE_VCN2_GPCOM_VCPU_DATA1 (0x505 << 2)
#define RDECODE_VCN2_ENGINE_CNTL (0x506 << 2)
#define RDECODE_VCN2_GPCOM_VCPU_CMD (0x503 << 2)
#define RDECODE_VCN2_GPCOM_VCPU_DATA0 (0x504 << 2)
#define RDECODE_VCN2_GPCOM_VCPU_DATA1 (0x505 << 2)
#define RDECODE_VCN2_GPCOM_VCPU_DATA2 (0x54C << 2)
#define RDECODE_VCN2_ENGINE_CNTL (0x506 << 2)
#define RDECODE_VCN2_5_GPCOM_VCPU_CMD 0x3c
#define RDECODE_VCN2_5_GPCOM_VCPU_DATA0 0x40
#define RDECODE_VCN2_5_GPCOM_VCPU_DATA1 0x44
#define RDECODE_VCN2_5_ENGINE_CNTL 0x9b4
#define RDECODE_VCN2_5_GPCOM_VCPU_CMD 0x3c
#define RDECODE_VCN2_5_GPCOM_VCPU_DATA0 0x40
#define RDECODE_VCN2_5_GPCOM_VCPU_DATA1 0x44
#define RDECODE_VCN2_5_GPCOM_VCPU_DATA2 0x1A0
#define RDECODE_VCN2_5_ENGINE_CNTL 0x9b4
#define RDECODE_SESSION_CONTEXT_SIZE (128 * 1024)

1
src/amd/vulkan/radv_physical_device.h
View file

@ -171,6 +171,7 @@ struct radv_physical_device {
struct {
unsigned data0;
unsigned data1;
unsigned data2;
unsigned cmd;
unsigned cntl;
} vid_dec_reg;

20
src/amd/vulkan/radv_video.c
View file

@ -35,6 +35,8 @@
/* Not 100% sure this isn't too much but works */
#define VID_DEFAULT_ALIGNMENT 256
static void set_reg(struct radv_cmd_buffer *cmd_buffer, unsigned reg, uint32_t val);
static bool
radv_enable_tier2(struct radv_physical_device *pdev)
{
@ -119,15 +121,19 @@ radv_vcn_write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *even
struct rvcn_sq_var sq;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
bool separate_queue = pdev->vid_decode_ip != AMD_IP_VCN_UNIFIED;
if (cmd_buffer->qf == RADV_QUEUE_VIDEO_DEC && separate_queue) {
// TODO: decode impl
return;
}
radv_cs_add_buffer(device->ws, cs, event->bo);
uint64_t va = radv_buffer_get_va(event->bo);
bool separate_queue = pdev->vid_decode_ip != AMD_IP_VCN_UNIFIED;
if (cmd_buffer->qf == RADV_QUEUE_VIDEO_DEC && separate_queue && pdev->vid_dec_reg.data2) {
radeon_check_space(device->ws, cmd_buffer->cs, 8);
set_reg(cmd_buffer, pdev->vid_dec_reg.data0, va & 0xffffffff);
set_reg(cmd_buffer, pdev->vid_dec_reg.data1, va >> 32);
set_reg(cmd_buffer, pdev->vid_dec_reg.data2, value);
set_reg(cmd_buffer, pdev->vid_dec_reg.cmd, RDECODE_CMD_WRITE_MEMORY << 1);
return;
}
radeon_check_space(device->ws, cs, 256);
radv_vcn_sq_header(cs, &sq, RADEON_VCN_ENGINE_TYPE_COMMON, separate_queue);
struct rvcn_cmn_engine_ib_package *ib_header = (struct rvcn_cmn_engine_ib_package *)&(cs->buf[cs->cdw]);
@ -205,6 +211,7 @@ init_vcn_decoder(struct radv_physical_device *pdev)
case VCN_2_2_0:
pdev->vid_dec_reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
pdev->vid_dec_reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
pdev->vid_dec_reg.data2 = RDECODE_VCN2_GPCOM_VCPU_DATA2;
pdev->vid_dec_reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
pdev->vid_dec_reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
break;
@ -218,6 +225,7 @@ init_vcn_decoder(struct radv_physical_device *pdev)
case VCN_3_1_2:
pdev->vid_dec_reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
pdev->vid_dec_reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
pdev->vid_dec_reg.data2 = RDECODE_VCN2_5_GPCOM_VCPU_DATA2;
pdev->vid_dec_reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
pdev->vid_dec_reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
break;