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gv100/ir: fix coherent and volatile memory access

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Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5747>
This commit is contained in:
Karol Herbst 2020-07-06 16:57:07 +02:00 • committed by Marge Bot
parent a43eb650de
commit 31e344799a
2 changed files with 10 additions and 15 deletions
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23
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp
View file

@ -991,21 +991,22 @@ CodeEmitterGV100::emitISBERD()
}
void
CodeEmitterGV100::emitLDSTc(int pos)
CodeEmitterGV100::emitLDSTc(int posm, int poso)
{
int mode = 0;
int order = 1;
switch (insn->cache) {
case CACHE_CA: mode = 0; break;
case CACHE_CG: mode = 1; break;
case CACHE_CS: mode = 2; break;
case CACHE_CV: mode = 3; break;
case CACHE_CA: mode = 0; order = 1; break;
case CACHE_CG: mode = 2; order = 2; break;
case CACHE_CV: mode = 3; order = 2; break;
default:
assert(!"invalid caching mode");
break;
}
emitField(pos, 2, mode);
emitField(poso, 2, order);
emitField(posm, 2, mode);
}
void
@ -1459,7 +1460,6 @@ CodeEmitterGV100::emitSULD()
assert(0);
break;
}
// emitLDSTc(0x18);
emitField(73, 3, type);
} else {
emitInsn(0x998);
@ -1468,7 +1468,7 @@ CodeEmitterGV100::emitSULD()
}
emitPRED (81);
emitField(79, 2, 1);
emitLDSTc(77, 79);
emitGPR (16, insn->def(0));
emitGPR (24, insn->src(0));
@ -1488,12 +1488,7 @@ CodeEmitterGV100::emitSUST()
#endif
emitSUTarget();
#if 0
emitLDSTc(0x18);
#endif
emitField(79, 2, 1);
emitLDSTc(77, 79);
emitField(72, 4, 0xf); // rgba
emitGPR(32, insn->src(1));
emitGPR(24, insn->src(0));

2
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.h
View file

@ -364,7 +364,7 @@ private:
void emitATOMS();
void emitIPA();
void emitISBERD();
void emitLDSTc(int);
void emitLDSTc(int, int);
void emitLDSTs(int, DataType);
void emitLD();
void emitLDC();