diff --git a/src/intel/compiler/brw_compile_fs.cpp b/src/intel/compiler/brw_compile_fs.cpp index bd8ad5d3cea..2f713509626 100644 --- a/src/intel/compiler/brw_compile_fs.cpp +++ b/src/intel/compiler/brw_compile_fs.cpp @@ -236,7 +236,7 @@ brw_emit_interpolation_setup(fs_visitor &s) * * The coarse pixel size is delivered as 2 u8 in r1.0 */ - struct brw_reg r1_0 = retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), BRW_TYPE_UB); + struct brw_reg r1_0 = retype(brw_vec1_reg(FIXED_GRF, 1, 0), BRW_TYPE_UB); const fs_builder dbld = abld.exec_all().group(MIN2(16, s.dispatch_width) * 2, 0); @@ -592,7 +592,7 @@ brw_emit_repclear_shader(fs_visitor &s) /* We pass the clear color as a flat input. Copy it to the output. */ brw_reg color_input = - brw_make_reg(BRW_GENERAL_REGISTER_FILE, 2, 3, 0, 0, BRW_TYPE_UD, + brw_make_reg(FIXED_GRF, 2, 3, 0, 0, BRW_TYPE_UD, BRW_VERTICAL_STRIDE_8, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_4, BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index 3e5741b03a9..982ae51bf17 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -246,9 +246,9 @@ static const char *const access_mode[2] = { }; static const char *const reg_file[4] = { - [BRW_ARCHITECTURE_REGISTER_FILE] = "A", - [BRW_GENERAL_REGISTER_FILE] = "g", - [BRW_IMMEDIATE_VALUE] = "imm", + [ARF] = "A", + [FIXED_GRF] = "g", + [IMM] = "imm", }; static const char *const writemask[16] = { @@ -779,7 +779,7 @@ reg(FILE *file, unsigned _reg_file, unsigned _reg_nr) { int err = 0; - if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) { + if (_reg_file == ARF) { switch (_reg_nr & 0xf0) { case BRW_ARF_NULL: string(file, "null"); @@ -923,9 +923,9 @@ dest_3src(FILE *file, const struct intel_device_info *devinfo, if (devinfo->ver >= 12) reg_file = brw_inst_3src_a1_dst_reg_file(devinfo, inst); else if (is_align1 && brw_inst_3src_a1_dst_reg_file(devinfo, inst)) - reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + reg_file = ARF; else - reg_file = BRW_GENERAL_REGISTER_FILE; + reg_file = FIXED_GRF; err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst)); if (err == -1) @@ -1218,7 +1218,7 @@ src0_3src(FILE *file, const struct intel_device_info *devinfo, if (is_align1) { _file = brw_inst_3src_a1_src0_reg_file(devinfo, inst); - if (_file == BRW_IMMEDIATE_VALUE) { + if (_file == IMM) { uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst); enum brw_reg_type type = brw_inst_3src_a1_src0_type(devinfo, inst); @@ -1241,7 +1241,7 @@ src0_3src(FILE *file, const struct intel_device_info *devinfo, brw_inst_3src_a1_src0_hstride(devinfo, inst)); _width = implied_width(_vert_stride, _horiz_stride); } else { - _file = BRW_GENERAL_REGISTER_FILE; + _file = FIXED_GRF; reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst); subreg_nr = brw_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4; type = brw_inst_3src_a16_src_type(devinfo, inst); @@ -1307,7 +1307,7 @@ src1_3src(FILE *file, const struct intel_device_info *devinfo, brw_inst_3src_a1_src1_hstride(devinfo, inst)); _width = implied_width(_vert_stride, _horiz_stride); } else { - _file = BRW_GENERAL_REGISTER_FILE; + _file = FIXED_GRF; reg_nr = brw_inst_3src_src1_reg_nr(devinfo, inst); subreg_nr = brw_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4; type = brw_inst_3src_a16_src_type(devinfo, inst); @@ -1363,7 +1363,7 @@ src2_3src(FILE *file, const struct intel_device_info *devinfo, if (is_align1) { _file = brw_inst_3src_a1_src2_reg_file(devinfo, inst); - if (_file == BRW_IMMEDIATE_VALUE) { + if (_file == IMM) { uint16_t imm_val = brw_inst_3src_a1_src2_imm(devinfo, inst); enum brw_reg_type type = brw_inst_3src_a1_src2_type(devinfo, inst); @@ -1390,7 +1390,7 @@ src2_3src(FILE *file, const struct intel_device_info *devinfo, brw_inst_3src_a1_src2_hstride(devinfo, inst)); _width = implied_width(_vert_stride, _horiz_stride); } else { - _file = BRW_GENERAL_REGISTER_FILE; + _file = FIXED_GRF; reg_nr = brw_inst_3src_src2_reg_nr(devinfo, inst); subreg_nr = brw_inst_3src_a16_src2_subreg_nr(devinfo, inst) * 4; type = brw_inst_3src_a16_src_type(devinfo, inst); @@ -1635,7 +1635,7 @@ src0(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) return src_sends_da(file, devinfo, BRW_TYPE_UD, - BRW_GENERAL_REGISTER_FILE, + FIXED_GRF, brw_inst_src0_da_reg_nr(devinfo, inst), brw_inst_src0_da16_subreg_nr(devinfo, inst)); } else { @@ -1645,7 +1645,7 @@ src0(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) brw_inst_send_src0_ia16_addr_imm(devinfo, inst), brw_inst_src0_ia_subreg_nr(devinfo, inst)); } - } else if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { + } else if (brw_inst_src0_reg_file(devinfo, inst) == IMM) { return imm(file, isa, brw_inst_src0_type(devinfo, inst), inst); } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { @@ -1709,7 +1709,7 @@ src1(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) brw_inst_send_src1_reg_file(devinfo, inst), brw_inst_send_src1_reg_nr(devinfo, inst), 0 /* subreg_nr */); - } else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { + } else if (brw_inst_src1_reg_file(devinfo, inst) == IMM) { return imm(file, isa, brw_inst_src1_type(devinfo, inst), inst); } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { @@ -1983,7 +1983,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, format(file, "x%d", rcount); } else if (!is_send(opcode) && (devinfo->ver < 12 || - brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE || + brw_inst_src0_reg_file(devinfo, inst) != IMM || brw_type_size_bytes(brw_inst_src0_type(devinfo, inst)) < 8)) { err |= control(file, "conditional modifier", conditional_modifier, brw_inst_cond_modifier(devinfo, inst), NULL); @@ -2097,7 +2097,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, fprintf(file, "0x%08"PRIx32, imm_ex_desc); } } else { - if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) { + if (brw_inst_src1_reg_file(devinfo, inst) != IMM) { /* show the indirect descriptor source */ pad(file, 48); err |= src1(file, isa, inst); diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c index 12efe3eeec9..c81525bb4fb 100644 --- a/src/intel/compiler/brw_eu_compact.c +++ b/src/intel/compiler/brw_eu_compact.c @@ -1571,10 +1571,10 @@ static bool has_immediate(const struct intel_device_info *devinfo, const brw_inst *inst, enum brw_reg_type *type) { - if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { + if (brw_inst_src0_reg_file(devinfo, inst) == IMM) { *type = brw_inst_src0_type(devinfo, inst); return *type != BRW_TYPE_INVALID; - } else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { + } else if (brw_inst_src1_reg_file(devinfo, inst) == IMM) { *type = brw_inst_src1_type(devinfo, inst); return *type != BRW_TYPE_INVALID; } @@ -1596,7 +1596,7 @@ precompact(const struct brw_isa_info *isa, brw_inst inst) * sequential elements, so convert to those before compacting. */ if (devinfo->verx10 >= 125) { - if (brw_inst_src0_reg_file(devinfo, &inst) == BRW_GENERAL_REGISTER_FILE && + if (brw_inst_src0_reg_file(devinfo, &inst) == FIXED_GRF && brw_inst_src0_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 && brw_inst_src0_vstride(devinfo, &inst) == (brw_inst_src0_width(devinfo, &inst) + 1) && brw_inst_src0_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) { @@ -1605,7 +1605,7 @@ precompact(const struct brw_isa_info *isa, brw_inst inst) brw_inst_set_src0_hstride(devinfo, &inst, BRW_HORIZONTAL_STRIDE_0); } - if (brw_inst_src1_reg_file(devinfo, &inst) == BRW_GENERAL_REGISTER_FILE && + if (brw_inst_src1_reg_file(devinfo, &inst) == FIXED_GRF && brw_inst_src1_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 && brw_inst_src1_vstride(devinfo, &inst) == (brw_inst_src1_width(devinfo, &inst) + 1) && brw_inst_src1_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) { @@ -1615,7 +1615,7 @@ precompact(const struct brw_isa_info *isa, brw_inst inst) } } - if (brw_inst_src0_reg_file(devinfo, &inst) != BRW_IMMEDIATE_VALUE) + if (brw_inst_src0_reg_file(devinfo, &inst) != IMM) return inst; /* The Bspec's section titled "Non-present Operands" claims that if src0 @@ -2441,9 +2441,9 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, if (brw_inst_cmpt_control(devinfo, insn)) break; - if (brw_inst_dst_reg_file(devinfo, insn) == BRW_ARCHITECTURE_REGISTER_FILE && + if (brw_inst_dst_reg_file(devinfo, insn) == ARF && brw_inst_dst_da_reg_nr(devinfo, insn) == BRW_ARF_IP) { - assert(brw_inst_src1_reg_file(devinfo, insn) == BRW_IMMEDIATE_VALUE); + assert(brw_inst_src1_reg_file(devinfo, insn) == IMM); int shift = 3; int jump_compacted = brw_inst_imm_d(devinfo, insn) >> shift; diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 9b368f6fa7f..382e5f89b3f 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -732,10 +732,6 @@ enum ENUM_PACKED brw_reg_file { VGRF, ATTR, UNIFORM, /* prog_data->params[reg] */ - - BRW_ARCHITECTURE_REGISTER_FILE = ARF, - BRW_GENERAL_REGISTER_FILE = FIXED_GRF, - BRW_IMMEDIATE_VALUE = IMM, }; /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 2b04b5ec661..bbdfcacc258 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -40,7 +40,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) { const struct intel_device_info *devinfo = p->devinfo; - if (dest.file == BRW_GENERAL_REGISTER_FILE) + if (dest.file == FIXED_GRF) assert(dest.nr < XE2_MAX_GRF); /* The hardware has a restriction where a destination of size Byte with @@ -48,7 +48,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) * instruction, the stride must be at least 2, even when the destination * is the NULL register. */ - if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE && + if (dest.file == ARF && dest.nr == BRW_ARF_NULL && brw_type_size_bytes(dest.type) == 1 && dest.hstride == BRW_HORIZONTAL_STRIDE_1) { @@ -58,8 +58,8 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) if (devinfo->ver >= 12 && (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND || brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC)) { - assert(dest.file == BRW_GENERAL_REGISTER_FILE || - dest.file == BRW_ARCHITECTURE_REGISTER_FILE); + assert(dest.file == FIXED_GRF || + dest.file == ARF); assert(dest.address_mode == BRW_ADDRESS_DIRECT); assert(dest.subnr == 0); assert(brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1 || @@ -72,8 +72,8 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS || brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC) { assert(devinfo->ver < 12); - assert(dest.file == BRW_GENERAL_REGISTER_FILE || - dest.file == BRW_ARCHITECTURE_REGISTER_FILE); + assert(dest.file == FIXED_GRF || + dest.file == ARF); assert(dest.address_mode == BRW_ADDRESS_DIRECT); assert(dest.subnr % 16 == 0); assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1 && @@ -97,7 +97,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) } else { brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16); brw_inst_set_da16_writemask(devinfo, inst, dest.writemask); - if (dest.file == BRW_GENERAL_REGISTER_FILE) { + if (dest.file == FIXED_GRF) { assert(dest.writemask != 0); } /* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1: @@ -132,7 +132,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) { const struct intel_device_info *devinfo = p->devinfo; - if (reg.file == BRW_GENERAL_REGISTER_FILE) + if (reg.file == FIXED_GRF) assert(reg.nr < XE2_MAX_GRF); if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND || @@ -151,7 +151,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) if (devinfo->ver >= 12 && (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND || brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC)) { - assert(reg.file != BRW_IMMEDIATE_VALUE); + assert(reg.file != IMM); assert(reg.address_mode == BRW_ADDRESS_DIRECT); assert(reg.subnr == 0); assert(has_scalar_region(reg) || @@ -163,7 +163,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS || brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC) { - assert(reg.file == BRW_GENERAL_REGISTER_FILE); + assert(reg.file == FIXED_GRF); assert(reg.address_mode == BRW_ADDRESS_DIRECT); assert(reg.subnr % 16 == 0); assert(has_scalar_region(reg) || @@ -178,7 +178,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) brw_inst_set_src0_negate(devinfo, inst, reg.negate); brw_inst_set_src0_address_mode(devinfo, inst, reg.address_mode); - if (reg.file == BRW_IMMEDIATE_VALUE) { + if (reg.file == IMM) { if (reg.type == BRW_TYPE_DF) brw_inst_set_imm_df(devinfo, inst, reg.df); else if (reg.type == BRW_TYPE_UQ || @@ -189,7 +189,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) if (devinfo->ver < 12 && brw_type_size_bytes(reg.type) < 8) { brw_inst_set_src1_reg_file(devinfo, inst, - BRW_ARCHITECTURE_REGISTER_FILE); + ARF); brw_inst_set_src1_reg_hw_type(devinfo, inst, brw_inst_src0_reg_hw_type(devinfo, inst)); } @@ -251,7 +251,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) { const struct intel_device_info *devinfo = p->devinfo; - if (reg.file == BRW_GENERAL_REGISTER_FILE) + if (reg.file == FIXED_GRF) assert(reg.nr < XE2_MAX_GRF); if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS || @@ -259,8 +259,8 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) (devinfo->ver >= 12 && (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND || brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC))) { - assert(reg.file == BRW_GENERAL_REGISTER_FILE || - reg.file == BRW_ARCHITECTURE_REGISTER_FILE); + assert(reg.file == FIXED_GRF || + reg.file == ARF); assert(reg.address_mode == BRW_ADDRESS_DIRECT); assert(reg.subnr == 0); assert(has_scalar_region(reg) || @@ -275,7 +275,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) * "Accumulator registers may be accessed explicitly as src0 * operands only." */ - assert(reg.file != BRW_ARCHITECTURE_REGISTER_FILE || + assert(reg.file != ARF || (reg.nr & 0xF0) != BRW_ARF_ACCUMULATOR); brw_inst_set_src1_file_type(devinfo, inst, reg.file, reg.type); @@ -284,9 +284,9 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) /* Only src1 can be immediate in two-argument instructions. */ - assert(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE); + assert(brw_inst_src0_reg_file(devinfo, inst) != IMM); - if (reg.file == BRW_IMMEDIATE_VALUE) { + if (reg.file == IMM) { /* two-argument instructions can only use 32-bit immediates */ assert(brw_type_size_bytes(reg.type) < 8); brw_inst_set_imm_ud(devinfo, inst, reg.ud); @@ -295,7 +295,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) * in the future: */ assert (reg.address_mode == BRW_ADDRESS_DIRECT); - /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */ + /* assert (reg.file == FIXED_GRF); */ brw_inst_set_src1_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { @@ -351,7 +351,7 @@ brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst, brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC); if (devinfo->ver < 12) brw_inst_set_src1_file_type(devinfo, inst, - BRW_IMMEDIATE_VALUE, BRW_TYPE_UD); + IMM, BRW_TYPE_UD); brw_inst_set_send_desc(devinfo, inst, desc); if (devinfo->ver >= 9) brw_inst_set_send_ex_desc(devinfo, inst, ex_desc); @@ -486,9 +486,9 @@ brw_alu2(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) { /* 64-bit immediates are only supported on 1-src instructions */ - assert(src0.file != BRW_IMMEDIATE_VALUE || + assert(src0.file != IMM || brw_type_size_bytes(src0.type) <= 4); - assert(src1.file != BRW_IMMEDIATE_VALUE || + assert(src1.file != IMM || brw_type_size_bytes(src1.type) <= 4); brw_inst *insn = next_insn(p, opcode); @@ -559,20 +559,20 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, assert(dest.nr < XE2_MAX_GRF); if (devinfo->ver >= 10) - assert(!(src0.file == BRW_IMMEDIATE_VALUE && - src2.file == BRW_IMMEDIATE_VALUE)); + assert(!(src0.file == IMM && + src2.file == IMM)); - assert(src0.file == BRW_IMMEDIATE_VALUE || src0.nr < XE2_MAX_GRF); - assert(src1.file != BRW_IMMEDIATE_VALUE && src1.nr < XE2_MAX_GRF); - assert(src2.file == BRW_IMMEDIATE_VALUE || src2.nr < XE2_MAX_GRF); + assert(src0.file == IMM || src0.nr < XE2_MAX_GRF); + assert(src1.file != IMM && src1.nr < XE2_MAX_GRF); + assert(src2.file == IMM || src2.nr < XE2_MAX_GRF); assert(dest.address_mode == BRW_ADDRESS_DIRECT); assert(src0.address_mode == BRW_ADDRESS_DIRECT); assert(src1.address_mode == BRW_ADDRESS_DIRECT); assert(src2.address_mode == BRW_ADDRESS_DIRECT); if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - assert(dest.file == BRW_GENERAL_REGISTER_FILE || - (dest.file == BRW_ARCHITECTURE_REGISTER_FILE && + assert(dest.file == FIXED_GRF || + (dest.file == ARF && (dest.nr & 0xF0) == BRW_ARF_ACCUMULATOR)); brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, dest.file); @@ -593,7 +593,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, brw_inst_set_3src_a1_src1_type(devinfo, inst, src1.type); brw_inst_set_3src_a1_src2_type(devinfo, inst, src2.type); - if (src0.file == BRW_IMMEDIATE_VALUE) { + if (src0.file == IMM) { brw_inst_set_3src_a1_src0_imm(devinfo, inst, src0.ud); } else { brw_inst_set_3src_a1_src0_vstride( @@ -611,7 +611,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, to_3src_align1_hstride(src1.hstride)); brw_inst_set_3src_a1_src1_subreg_nr(devinfo, inst, phys_subnr(devinfo, src1)); - if (src1.file == BRW_ARCHITECTURE_REGISTER_FILE) { + if (src1.file == ARF) { brw_inst_set_3src_src1_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR); } else { brw_inst_set_3src_src1_reg_nr(devinfo, inst, phys_nr(devinfo, src1)); @@ -619,7 +619,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, brw_inst_set_3src_src1_abs(devinfo, inst, src1.abs); brw_inst_set_3src_src1_negate(devinfo, inst, src1.negate); - if (src2.file == BRW_IMMEDIATE_VALUE) { + if (src2.file == IMM) { brw_inst_set_3src_a1_src2_imm(devinfo, inst, src2.ud); } else { brw_inst_set_3src_a1_src2_hstride(devinfo, inst, @@ -631,16 +631,16 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, brw_inst_set_3src_src2_negate(devinfo, inst, src2.negate); } - assert(src0.file == BRW_GENERAL_REGISTER_FILE || - src0.file == BRW_IMMEDIATE_VALUE); - assert(src1.file == BRW_GENERAL_REGISTER_FILE || - (src1.file == BRW_ARCHITECTURE_REGISTER_FILE && + assert(src0.file == FIXED_GRF || + src0.file == IMM); + assert(src1.file == FIXED_GRF || + (src1.file == ARF && src1.nr == BRW_ARF_ACCUMULATOR)); - assert(src2.file == BRW_GENERAL_REGISTER_FILE || - src2.file == BRW_IMMEDIATE_VALUE); + assert(src2.file == FIXED_GRF || + src2.file == IMM); if (devinfo->ver >= 12) { - if (src0.file == BRW_IMMEDIATE_VALUE) { + if (src0.file == IMM) { brw_inst_set_3src_a1_src0_is_imm(devinfo, inst, 1); } else { brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file); @@ -648,7 +648,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, brw_inst_set_3src_a1_src1_reg_file(devinfo, inst, src1.file); - if (src2.file == BRW_IMMEDIATE_VALUE) { + if (src2.file == IMM) { brw_inst_set_3src_a1_src2_is_imm(devinfo, inst, 1); } else { brw_inst_set_3src_a1_src2_reg_file(devinfo, inst, src2.file); @@ -660,7 +660,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, } } else { - assert(dest.file == BRW_GENERAL_REGISTER_FILE); + assert(dest.file == FIXED_GRF); assert(dest.type == BRW_TYPE_F || dest.type == BRW_TYPE_DF || dest.type == BRW_TYPE_D || @@ -670,7 +670,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, brw_inst_set_3src_a16_dst_subreg_nr(devinfo, inst, dest.subnr / 4); brw_inst_set_3src_a16_dst_writemask(devinfo, inst, dest.writemask); - assert(src0.file == BRW_GENERAL_REGISTER_FILE); + assert(src0.file == FIXED_GRF); brw_inst_set_3src_a16_src0_swizzle(devinfo, inst, src0.swizzle); brw_inst_set_3src_a16_src0_subreg_nr(devinfo, inst, get_3src_subreg_nr(src0)); brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr); @@ -679,7 +679,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, brw_inst_set_3src_a16_src0_rep_ctrl(devinfo, inst, src0.vstride == BRW_VERTICAL_STRIDE_0); - assert(src1.file == BRW_GENERAL_REGISTER_FILE); + assert(src1.file == FIXED_GRF); brw_inst_set_3src_a16_src1_swizzle(devinfo, inst, src1.swizzle); brw_inst_set_3src_a16_src1_subreg_nr(devinfo, inst, get_3src_subreg_nr(src1)); brw_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr); @@ -688,7 +688,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, brw_inst_set_3src_a16_src1_rep_ctrl(devinfo, inst, src1.vstride == BRW_VERTICAL_STRIDE_0); - assert(src2.file == BRW_GENERAL_REGISTER_FILE); + assert(src2.file == FIXED_GRF); brw_inst_set_3src_a16_src2_swizzle(devinfo, inst, src2.swizzle); brw_inst_set_3src_a16_src2_subreg_nr(devinfo, inst, get_3src_subreg_nr(src2)); brw_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr); @@ -734,9 +734,9 @@ brw_dpas_three_src(struct brw_codegen *p, enum opcode opcode, const struct intel_device_info *devinfo = p->devinfo; brw_inst *inst = next_insn(p, opcode); - assert(dest.file == BRW_GENERAL_REGISTER_FILE); + assert(dest.file == FIXED_GRF); brw_inst_set_dpas_3src_dst_reg_file(devinfo, inst, - BRW_GENERAL_REGISTER_FILE); + FIXED_GRF); brw_inst_set_dpas_3src_dst_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); brw_inst_set_dpas_3src_dst_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest)); @@ -756,22 +756,22 @@ brw_dpas_three_src(struct brw_codegen *p, enum opcode opcode, brw_inst_set_dpas_3src_src1_type(devinfo, inst, src1.type); brw_inst_set_dpas_3src_src2_type(devinfo, inst, src2.type); - assert(src0.file == BRW_GENERAL_REGISTER_FILE || - (src0.file == BRW_ARCHITECTURE_REGISTER_FILE && + assert(src0.file == FIXED_GRF || + (src0.file == ARF && src0.nr == BRW_ARF_NULL)); brw_inst_set_dpas_3src_src0_reg_file(devinfo, inst, src0.file); brw_inst_set_dpas_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0)); brw_inst_set_dpas_3src_src0_subreg_nr(devinfo, inst, phys_subnr(devinfo, src0)); - assert(src1.file == BRW_GENERAL_REGISTER_FILE); + assert(src1.file == FIXED_GRF); brw_inst_set_dpas_3src_src1_reg_file(devinfo, inst, src1.file); brw_inst_set_dpas_3src_src1_reg_nr(devinfo, inst, phys_nr(devinfo, src1)); brw_inst_set_dpas_3src_src1_subreg_nr(devinfo, inst, phys_subnr(devinfo, src1)); brw_inst_set_dpas_3src_src1_subbyte(devinfo, inst, BRW_SUB_BYTE_PRECISION_NONE); - assert(src2.file == BRW_GENERAL_REGISTER_FILE); + assert(src2.file == FIXED_GRF); brw_inst_set_dpas_3src_src2_reg_file(devinfo, inst, src2.file); brw_inst_set_dpas_3src_src2_reg_nr(devinfo, inst, phys_nr(devinfo, src2)); @@ -893,14 +893,14 @@ brw_ADD(struct brw_codegen *p, struct brw_reg dest, { /* 6.2.2: add */ if (src0.type == BRW_TYPE_F || - (src0.file == BRW_IMMEDIATE_VALUE && + (src0.file == IMM && src0.type == BRW_TYPE_VF)) { assert(src1.type != BRW_TYPE_UD); assert(src1.type != BRW_TYPE_D); } if (src1.type == BRW_TYPE_F || - (src1.file == BRW_IMMEDIATE_VALUE && + (src1.file == IMM && src1.type == BRW_TYPE_VF)) { assert(src0.type != BRW_TYPE_UD); assert(src0.type != BRW_TYPE_D); @@ -943,22 +943,22 @@ brw_MUL(struct brw_codegen *p, struct brw_reg dest, } if (src0.type == BRW_TYPE_F || - (src0.file == BRW_IMMEDIATE_VALUE && + (src0.file == IMM && src0.type == BRW_TYPE_VF)) { assert(src1.type != BRW_TYPE_UD); assert(src1.type != BRW_TYPE_D); } if (src1.type == BRW_TYPE_F || - (src1.file == BRW_IMMEDIATE_VALUE && + (src1.file == IMM && src1.type == BRW_TYPE_VF)) { assert(src0.type != BRW_TYPE_UD); assert(src0.type != BRW_TYPE_D); } - assert(src0.file != BRW_ARCHITECTURE_REGISTER_FILE || + assert(src0.file != ARF || src0.nr != BRW_ARF_ACCUMULATOR); - assert(src1.file != BRW_ARCHITECTURE_REGISTER_FILE || + assert(src1.file != ARF || src1.nr != BRW_ARF_ACCUMULATOR); return brw_alu2(p, BRW_OPCODE_MUL, dest, src0, src1); @@ -1363,7 +1363,7 @@ void gfx6_math(struct brw_codegen *p, const struct intel_device_info *devinfo = p->devinfo; brw_inst *insn = next_insn(p, BRW_OPCODE_MATH); - assert(dest.file == BRW_GENERAL_REGISTER_FILE); + assert(dest.file == FIXED_GRF); assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1); @@ -1372,8 +1372,8 @@ void gfx6_math(struct brw_codegen *p, function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) { assert(src0.type != BRW_TYPE_F); assert(src1.type != BRW_TYPE_F); - assert(src1.file == BRW_GENERAL_REGISTER_FILE || - src1.file == BRW_IMMEDIATE_VALUE); + assert(src1.file == FIXED_GRF || + src1.file == IMM); /* From BSpec 6647/47428 "[Instruction] Extended Math Function": * INT DIV function does not support source modifiers. */ @@ -1411,7 +1411,7 @@ brw_send_indirect_message(struct brw_codegen *p, assert(desc.type == BRW_TYPE_UD); - if (desc.file == BRW_IMMEDIATE_VALUE) { + if (desc.file == IMM) { send = next_insn(p, BRW_OPCODE_SEND); brw_set_src0(p, send, retype(payload, BRW_TYPE_UD)); brw_set_desc(p, send, desc.ud | desc_imm); @@ -1471,7 +1471,7 @@ brw_send_indirect_split_message(struct brw_codegen *p, assert(desc.type == BRW_TYPE_UD); - if (desc.file == BRW_IMMEDIATE_VALUE) { + if (desc.file == IMM) { desc.ud |= desc_imm; } else { const struct tgl_swsb swsb = brw_get_default_swsb(p); @@ -1497,7 +1497,7 @@ brw_send_indirect_split_message(struct brw_codegen *p, brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); } - if (ex_desc.file == BRW_IMMEDIATE_VALUE && + if (ex_desc.file == IMM && !ex_desc_scratch && (devinfo->ver >= 12 || ((ex_desc.ud | ex_desc_imm) & INTEL_MASK(15, 12)) == 0)) { @@ -1554,7 +1554,7 @@ brw_send_indirect_split_message(struct brw_codegen *p, brw_OR(p, addr, addr, brw_imm_ud(imm_part)); } - } else if (ex_desc.file == BRW_IMMEDIATE_VALUE) { + } else if (ex_desc.file == IMM) { /* ex_desc bits 15:12 don't exist in the instruction encoding prior * to Gfx12, so we may have fallen back to an indirect extended * descriptor. @@ -1575,21 +1575,21 @@ brw_send_indirect_split_message(struct brw_codegen *p, brw_set_src0(p, send, retype(payload0, BRW_TYPE_UD)); brw_set_src1(p, send, retype(payload1, BRW_TYPE_UD)); - if (desc.file == BRW_IMMEDIATE_VALUE) { + if (desc.file == IMM) { brw_inst_set_send_sel_reg32_desc(devinfo, send, 0); brw_inst_set_send_desc(devinfo, send, desc.ud); } else { - assert(desc.file == BRW_ARCHITECTURE_REGISTER_FILE); + assert(desc.file == ARF); assert(desc.nr == BRW_ARF_ADDRESS); assert(desc.subnr == 0); brw_inst_set_send_sel_reg32_desc(devinfo, send, 1); } - if (ex_desc.file == BRW_IMMEDIATE_VALUE) { + if (ex_desc.file == IMM) { brw_inst_set_send_sel_reg32_ex_desc(devinfo, send, 0); brw_inst_set_sends_ex_desc(devinfo, send, ex_desc.ud); } else { - assert(ex_desc.file == BRW_ARCHITECTURE_REGISTER_FILE); + assert(ex_desc.file == ARF); assert(ex_desc.nr == BRW_ARF_ADDRESS); assert((ex_desc.subnr & 0x3) == 0); brw_inst_set_send_sel_reg32_ex_desc(devinfo, send, 1); @@ -1896,7 +1896,7 @@ brw_broadcast(struct brw_codegen *p, brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_exec_size(p, BRW_EXECUTE_1); - assert(src.file == BRW_GENERAL_REGISTER_FILE && + assert(src.file == FIXED_GRF && src.address_mode == BRW_ADDRESS_DIRECT); assert(!src.abs && !src.negate); @@ -1913,12 +1913,12 @@ brw_broadcast(struct brw_codegen *p, brw_type_with_size(BRW_TYPE_UD, brw_type_size_bits(src.type)); if ((src.vstride == 0 && src.hstride == 0) || - idx.file == BRW_IMMEDIATE_VALUE) { + idx.file == IMM) { /* Trivial, the source is already uniform or the index is a constant. * We will typically not get here if the optimizer is doing its job, but * asserting would be mean. */ - const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0; + const unsigned i = idx.file == IMM ? idx.ud : 0; src = stride(suboffset(src, i), 0, 1, 0); if (brw_type_size_bytes(src.type) > 4 && !devinfo->has_64bit_int) { @@ -2101,7 +2101,7 @@ brw_update_reloc_imm(const struct brw_isa_info *isa, /* Sanity check that the instruction is a MOV of an immediate */ assert(brw_inst_opcode(isa, inst) == BRW_OPCODE_MOV); - assert(brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE); + assert(brw_inst_src0_reg_file(devinfo, inst) == IMM); /* If it was compacted, we can't safely rewrite */ assert(brw_inst_cmpt_control(devinfo, inst) == 0); diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index 709e0cca58d..dc38dc399f1 100644 --- a/src/intel/compiler/brw_eu_validate.c +++ b/src/intel/compiler/brw_eu_validate.c @@ -145,7 +145,7 @@ inst_is_raw_move(const struct brw_isa_info *isa, const brw_inst *inst) unsigned dst_type = signed_type(inst_dst_type(isa, inst)); unsigned src_type = signed_type(brw_inst_src0_type(devinfo, inst)); - if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { + if (brw_inst_src0_reg_file(devinfo, inst) == IMM) { /* FIXME: not strictly true */ if (brw_inst_src0_type(devinfo, inst) == BRW_TYPE_VF || brw_inst_src0_type(devinfo, inst) == BRW_TYPE_UV || @@ -165,7 +165,7 @@ inst_is_raw_move(const struct brw_isa_info *isa, const brw_inst *inst) static bool dst_is_null(const struct intel_device_info *devinfo, const brw_inst *inst) { - return brw_inst_dst_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && + return brw_inst_dst_reg_file(devinfo, inst) == ARF && brw_inst_dst_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; } @@ -173,28 +173,28 @@ static bool src0_is_null(const struct intel_device_info *devinfo, const brw_inst *inst) { return brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT && - brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && + brw_inst_src0_reg_file(devinfo, inst) == ARF && brw_inst_src0_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; } static bool src1_is_null(const struct intel_device_info *devinfo, const brw_inst *inst) { - return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && + return brw_inst_src1_reg_file(devinfo, inst) == ARF && brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; } static bool src0_is_acc(const struct intel_device_info *devinfo, const brw_inst *inst) { - return brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && + return brw_inst_src0_reg_file(devinfo, inst) == ARF && (brw_inst_src0_da_reg_nr(devinfo, inst) & 0xF0) == BRW_ARF_ACCUMULATOR; } static bool src1_is_acc(const struct intel_device_info *devinfo, const brw_inst *inst) { - return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && + return brw_inst_src1_reg_file(devinfo, inst) == ARF && (brw_inst_src1_da_reg_nr(devinfo, inst) & 0xF0) == BRW_ARF_ACCUMULATOR; } @@ -358,7 +358,7 @@ send_restrictions(const struct brw_isa_info *isa, struct string error_msg = { .str = NULL, .len = 0 }; if (inst_is_split_send(isa, inst)) { - ERROR_IF(brw_inst_send_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && + ERROR_IF(brw_inst_send_src1_reg_file(devinfo, inst) == ARF && brw_inst_send_src1_reg_nr(devinfo, inst) != BRW_ARF_NULL, "src1 of split send must be a GRF or NULL"); @@ -366,12 +366,12 @@ send_restrictions(const struct brw_isa_info *isa, brw_inst_src0_da_reg_nr(devinfo, inst) < 112, "send with EOT must use g112-g127"); ERROR_IF(brw_inst_eot(devinfo, inst) && - brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE && + brw_inst_send_src1_reg_file(devinfo, inst) == FIXED_GRF && brw_inst_send_src1_reg_nr(devinfo, inst) < 112, "send with EOT must use g112-g127"); - if (brw_inst_send_src0_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE && - brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE) { + if (brw_inst_send_src0_reg_file(devinfo, inst) == FIXED_GRF && + brw_inst_send_src1_reg_file(devinfo, inst) == FIXED_GRF) { /* Assume minimums if we don't know */ unsigned mlen = 1; if (!brw_inst_send_sel_reg32_desc(devinfo, inst)) { @@ -397,7 +397,7 @@ send_restrictions(const struct brw_isa_info *isa, ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT, "send must use direct addressing"); - ERROR_IF(brw_inst_send_src0_reg_file(devinfo, inst) != BRW_GENERAL_REGISTER_FILE, + ERROR_IF(brw_inst_send_src0_reg_file(devinfo, inst) != FIXED_GRF, "send from non-GRF"); ERROR_IF(brw_inst_eot(devinfo, inst) && brw_inst_src0_da_reg_nr(devinfo, inst) < 112, @@ -993,7 +993,7 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa, "Destination Horizontal Stride must be 1"); if (num_sources >= 1) { - ERROR_IF(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && + ERROR_IF(brw_inst_src0_reg_file(devinfo, inst) != IMM && brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 && brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, @@ -1001,7 +1001,7 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa, } if (num_sources == 2) { - ERROR_IF(brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && + ERROR_IF(brw_inst_src1_reg_file(devinfo, inst) != IMM && brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 && brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, @@ -1017,7 +1017,7 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa, #define DO_SRC(n) \ if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \ - BRW_IMMEDIATE_VALUE) \ + IMM) \ continue; \ \ vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \ @@ -1457,7 +1457,7 @@ region_alignment_rules(const struct brw_isa_info *isa, continue; \ \ if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \ - BRW_IMMEDIATE_VALUE) \ + IMM) \ continue; \ \ vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \ @@ -1554,7 +1554,7 @@ vector_immediate_restrictions(const struct brw_isa_info *isa, unsigned file = num_sources == 1 ? brw_inst_src0_reg_file(devinfo, inst) : brw_inst_src1_reg_file(devinfo, inst); - if (file != BRW_IMMEDIATE_VALUE) + if (file != IMM) return (struct string){}; enum brw_reg_type dst_type = inst_dst_type(isa, inst); @@ -1648,7 +1648,7 @@ special_requirements_for_handling_double_precision_data_types( #define DO_SRC(n) \ if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \ - BRW_IMMEDIATE_VALUE) \ + IMM) \ continue; \ \ is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \ @@ -1732,9 +1732,9 @@ special_requirements_for_handling_double_precision_data_types( intel_device_info_is_9lp(devinfo)) { ERROR_IF(brw_inst_opcode(isa, inst) == BRW_OPCODE_MAC || brw_inst_acc_wr_control(devinfo, inst) || - (BRW_ARCHITECTURE_REGISTER_FILE == file && + (ARF == file && reg != BRW_ARF_NULL) || - (BRW_ARCHITECTURE_REGISTER_FILE == dst_file && + (ARF == dst_file && dst_reg != BRW_ARF_NULL), "Architecture registers cannot be used when the execution " "type is 64-bit"); @@ -1772,9 +1772,9 @@ special_requirements_for_handling_double_precision_data_types( "source and destination are not supported except for " "broadcast of a scalar."); - ERROR_IF((address_mode == BRW_ADDRESS_DIRECT && file == BRW_ARCHITECTURE_REGISTER_FILE && + ERROR_IF((address_mode == BRW_ADDRESS_DIRECT && file == ARF && reg != BRW_ARF_NULL && !(reg >= BRW_ARF_ACCUMULATOR && reg < BRW_ARF_FLAG)) || - (dst_file == BRW_ARCHITECTURE_REGISTER_FILE && + (dst_file == ARF && dst_reg != BRW_ARF_NULL && (dst_reg & 0xF0) != BRW_ARF_ACCUMULATOR), "Explicit ARF registers except null and accumulator must not " "be used."); @@ -1850,12 +1850,12 @@ instruction_restrictions(const struct brw_isa_info *isa, enum brw_reg_type exec_type = execution_type(isa, inst); const bool src0_valid = brw_type_size_bytes(brw_inst_src0_type(devinfo, inst)) == 4 || - brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE || + brw_inst_src0_reg_file(devinfo, inst) == IMM || !(brw_inst_src0_negate(devinfo, inst) || brw_inst_src0_abs(devinfo, inst)); const bool src1_valid = brw_type_size_bytes(brw_inst_src1_type(devinfo, inst)) == 4 || - brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE || + brw_inst_src1_reg_file(devinfo, inst) == IMM || !(brw_inst_src1_negate(devinfo, inst) || brw_inst_src1_abs(devinfo, inst)); @@ -2029,7 +2029,7 @@ instruction_restrictions(const struct brw_isa_info *isa, ERROR_IF(brw_inst_src0_abs(devinfo, inst), "Behavior of abs source modifier in logic ops is undefined."); ERROR_IF(brw_inst_opcode(isa, inst) != BRW_OPCODE_NOT && - brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && + brw_inst_src1_reg_file(devinfo, inst) != IMM && brw_inst_src1_abs(devinfo, inst), "Behavior of abs source modifier in logic ops is undefined."); @@ -2337,7 +2337,7 @@ send_descriptor_restrictions(const struct brw_isa_info *isa, return error_msg; } else if (inst_is_send(isa, inst)) { /* We can only validate immediate descriptors */ - if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) + if (brw_inst_src1_reg_file(devinfo, inst) != IMM) return error_msg; } else { return error_msg; diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 0e75755ee7f..41f91e72dec 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -174,7 +174,7 @@ fs_generator::generate_send(fs_inst *inst, uint32_t ex_desc_imm = inst->ex_desc | brw_message_ex_desc(devinfo, inst->ex_mlen); - if (ex_desc.file != BRW_IMMEDIATE_VALUE || ex_desc.ud || ex_desc_imm || + if (ex_desc.file != IMM || ex_desc.ud || ex_desc_imm || inst->send_ex_desc_scratch) { /* If we have any sort of extended descriptor, then we need SENDS. This * also covers the dual-payload case because ex_mlen goes in ex_desc. @@ -201,7 +201,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst, struct brw_reg indirect_byte_offset) { assert(indirect_byte_offset.type == BRW_TYPE_UD); - assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE); + assert(indirect_byte_offset.file == FIXED_GRF); assert(!reg.abs && !reg.negate); /* Gen12.5 adds the following region restriction: @@ -218,7 +218,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst, unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr; - if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) { + if (indirect_byte_offset.file == IMM) { imm_byte_offset += indirect_byte_offset.ud; reg.nr = imm_byte_offset / REG_SIZE; @@ -331,7 +331,7 @@ fs_generator::generate_shuffle(fs_inst *inst, struct brw_reg src, struct brw_reg idx) { - assert(src.file == BRW_GENERAL_REGISTER_FILE); + assert(src.file == FIXED_GRF); assert(!src.abs && !src.negate); /* Ivy bridge has some strange behavior that makes this a real pain to @@ -367,12 +367,12 @@ fs_generator::generate_shuffle(fs_inst *inst, brw_set_default_group(p, group); if ((src.vstride == 0 && src.hstride == 0) || - idx.file == BRW_IMMEDIATE_VALUE) { + idx.file == IMM) { /* Trivial, the source is already uniform or the index is a constant. * We will typically not get here if the optimizer is doing its job, * but asserting would be mean. */ - const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0; + const unsigned i = idx.file == IMM ? idx.ud : 0; struct brw_reg group_src = stride(suboffset(src, i), 0, 1, 0); struct brw_reg group_dst = suboffset(dst, group << (dst.hstride - 1)); brw_MOV(p, group_dst, group_src); @@ -463,7 +463,7 @@ fs_generator::generate_quad_swizzle(const fs_inst *inst, /* Requires a quad. */ assert(inst->exec_size >= 4); - if (src.file == BRW_IMMEDIATE_VALUE || + if (src.file == IMM || has_scalar_region(src)) { /* The value is uniform across all channels */ brw_MOV(p, dst, src); @@ -706,8 +706,8 @@ fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg src) { assert(inst->exec_size == 8 && inst->force_writemask_all); - assert(dst.file == BRW_GENERAL_REGISTER_FILE); - assert(src.file == BRW_GENERAL_REGISTER_FILE); + assert(dst.file == FIXED_GRF); + assert(src.file == FIXED_GRF); assert(src.type == BRW_TYPE_UD); dst.type = BRW_TYPE_UD; @@ -907,7 +907,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, brw_NOP(p); break; case BRW_OPCODE_SYNC: - assert(src[0].file == BRW_IMMEDIATE_VALUE); + assert(src[0].file == IMM); brw_SYNC(p, tgl_sync_function(src[0].ud)); if (tgl_sync_function(src[0].ud) == TGL_SYNC_NOP) @@ -1124,7 +1124,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, assert(src[0].type == BRW_TYPE_UW); assert(src[1].type == BRW_TYPE_UW); src[0].subnr = 0 * brw_type_size_bytes(src[0].type); - if (src[1].file == BRW_IMMEDIATE_VALUE) { + if (src[1].file == IMM) { assert(src[1].ud == 0); brw_MOV(p, dst, stride(src[0], 8, 4, 1)); } else { @@ -1136,7 +1136,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, assert(src[0].type == BRW_TYPE_UW); assert(src[1].type == BRW_TYPE_UW); src[0].subnr = 4 * brw_type_size_bytes(src[0].type); - if (src[1].file == BRW_IMMEDIATE_VALUE) { + if (src[1].file == IMM) { assert(src[1].ud == 0); brw_MOV(p, dst, stride(src[0], 8, 4, 1)); } else { @@ -1169,8 +1169,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, break; case SHADER_OPCODE_MOV_RELOC_IMM: - assert(src[0].file == BRW_IMMEDIATE_VALUE); - assert(src[1].file == BRW_IMMEDIATE_VALUE); + assert(src[0].file == IMM); + assert(src[1].file == IMM); brw_MOV_reloc_imm(p, dst, dst.type, src[0].ud, src[1].ud); break; @@ -1180,8 +1180,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, case SHADER_OPCODE_INTERLOCK: case SHADER_OPCODE_MEMORY_FENCE: { - assert(src[1].file == BRW_IMMEDIATE_VALUE); - assert(src[2].file == BRW_IMMEDIATE_VALUE); + assert(src[1].file == IMM); + assert(src[2].file == IMM); const enum opcode send_op = inst->opcode == SHADER_OPCODE_INTERLOCK ? BRW_OPCODE_SENDC : BRW_OPCODE_SEND; @@ -1259,7 +1259,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, break; case SHADER_OPCODE_QUAD_SWIZZLE: - assert(src[1].file == BRW_IMMEDIATE_VALUE); + assert(src[1].file == IMM); assert(src[1].type == BRW_TYPE_UD); generate_quad_swizzle(inst, dst, src[0], src[1].ud); break; @@ -1268,9 +1268,9 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, assert((!intel_device_info_is_9lp(devinfo) && devinfo->has_64bit_float) || brw_type_size_bytes(src[0].type) <= 4); assert(!src[0].negate && !src[0].abs); - assert(src[1].file == BRW_IMMEDIATE_VALUE); + assert(src[1].file == IMM); assert(src[1].type == BRW_TYPE_UD); - assert(src[2].file == BRW_IMMEDIATE_VALUE); + assert(src[2].file == IMM); assert(src[2].type == BRW_TYPE_UD); const unsigned component = src[1].ud; const unsigned cluster_size = src[2].ud; @@ -1314,7 +1314,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, break; case SHADER_OPCODE_RND_MODE: { - assert(src[0].file == BRW_IMMEDIATE_VALUE); + assert(src[0].file == IMM); /* * Changes the floating point rounding mode updating the control * register field defined at cr0.0[5-6] bits. @@ -1326,8 +1326,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, break; case SHADER_OPCODE_FLOAT_CONTROL_MODE: - assert(src[0].file == BRW_IMMEDIATE_VALUE); - assert(src[1].file == BRW_IMMEDIATE_VALUE); + assert(src[0].file == IMM); + assert(src[1].file == IMM); brw_float_controls_mode(p, src[0].d, src[1].d); break; diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index aa95cf0fa4c..7a4a25e16b5 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -3447,7 +3447,7 @@ fetch_render_target_array_index(const fs_builder &bld) for (unsigned i = 0; i < v->max_polygons; i++) { const fs_builder hbld = bld.group(8, i); - const struct brw_reg g1 = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 3 + 10 * i); + const struct brw_reg g1 = brw_uw1_reg(FIXED_GRF, 1, 3 + 10 * i); hbld.AND(offset(idx, hbld, i), g1, brw_imm_uw(0x7ff)); } @@ -3457,7 +3457,7 @@ fetch_render_target_array_index(const fs_builder &bld) * bits 26:16 of r1.1. */ const brw_reg idx = bld.vgrf(BRW_TYPE_UD); - bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 3), + bld.AND(idx, brw_uw1_reg(FIXED_GRF, 1, 3), brw_imm_uw(0x7ff)); return idx; } else { @@ -3465,7 +3465,7 @@ fetch_render_target_array_index(const fs_builder &bld) * bits 26:16 of r0.0. */ const brw_reg idx = bld.vgrf(BRW_TYPE_UD); - bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 0, 1), + bld.AND(idx, brw_uw1_reg(FIXED_GRF, 0, 1), brw_imm_uw(0x7ff)); return idx; } @@ -3504,8 +3504,8 @@ fetch_viewport_index(const fs_builder &bld) assert(bld.dispatch_width() == 16); const brw_reg idx = bld.vgrf(BRW_TYPE_UD); brw_reg vp_idx_per_poly_dw[2] = { - brw_ud1_reg(BRW_GENERAL_REGISTER_FILE, 1, 1), /* R1.1 bits 30:27 */ - brw_ud1_reg(BRW_GENERAL_REGISTER_FILE, 1, 6), /* R1.6 bits 30:27 */ + brw_ud1_reg(FIXED_GRF, 1, 1), /* R1.1 bits 30:27 */ + brw_ud1_reg(FIXED_GRF, 1, 6), /* R1.6 bits 30:27 */ }; for (unsigned i = 0; i < v->max_polygons; i++) { @@ -3520,7 +3520,7 @@ fetch_viewport_index(const fs_builder &bld) */ const brw_reg idx = bld.vgrf(BRW_TYPE_UD); bld.SHR(idx, - bld.AND(brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 3), + bld.AND(brw_uw1_reg(FIXED_GRF, 1, 3), brw_imm_uw(0x7800)), brw_imm_ud(11)); return idx; @@ -3530,7 +3530,7 @@ fetch_viewport_index(const fs_builder &bld) */ const brw_reg idx = bld.vgrf(BRW_TYPE_UD); bld.SHR(idx, - bld.AND(brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 0, 1), + bld.AND(brw_uw1_reg(FIXED_GRF, 0, 1), brw_imm_uw(0x7800)), brw_imm_ud(11)); return idx; @@ -5356,7 +5356,7 @@ get_timestamp(const fs_builder &bld) { fs_visitor &s = *bld.shader; - brw_reg ts = brw_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE, + brw_reg ts = brw_reg(retype(brw_vec4_reg(ARF, BRW_ARF_TIMESTAMP, 0), BRW_TYPE_UD)); brw_reg dst = brw_vgrf(s.alloc.allocate(1), BRW_TYPE_UD); @@ -8467,7 +8467,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, /* If mcs is an immediate value, it means there is no MCS. In that case * just return false. */ - if (srcs[TEX_LOGICAL_SRC_MCS].file == BRW_IMMEDIATE_VALUE) { + if (srcs[TEX_LOGICAL_SRC_MCS].file == IMM) { bld.MOV(dst, brw_imm_ud(0u)); } else { brw_reg tmp = diff --git a/src/intel/compiler/brw_fs_opt.cpp b/src/intel/compiler/brw_fs_opt.cpp index f2c0da89798..ebb86e4a19b 100644 --- a/src/intel/compiler/brw_fs_opt.cpp +++ b/src/intel/compiler/brw_fs_opt.cpp @@ -501,7 +501,7 @@ brw_fs_opt_remove_extra_rounding_modes(fs_visitor &s) foreach_inst_in_block_safe (fs_inst, inst, block) { if (inst->opcode == SHADER_OPCODE_RND_MODE) { - assert(inst->src[0].file == BRW_IMMEDIATE_VALUE); + assert(inst->src[0].file == IMM); const brw_rnd_mode mode = (brw_rnd_mode) inst->src[0].d; if (mode == prev_mode) { inst->remove(block); diff --git a/src/intel/compiler/brw_fs_validate.cpp b/src/intel/compiler/brw_fs_validate.cpp index 7d320383005..b3544108411 100644 --- a/src/intel/compiler/brw_fs_validate.cpp +++ b/src/intel/compiler/brw_fs_validate.cpp @@ -134,7 +134,7 @@ brw_fs_validate(const fs_visitor &s) if (devinfo->ver >= 10) { for (unsigned i = 0; i < 3; i++) { - if (inst->src[i].file == BRW_IMMEDIATE_VALUE) + if (inst->src[i].file == IMM) continue; switch (inst->src[i].vstride) { @@ -166,7 +166,7 @@ brw_fs_validate(const fs_visitor &s) * passes (e.g., combine constants) will fix them. */ for (unsigned i = 0; i < 3; i++) { - fsv_assert_ne(inst->src[i].file, BRW_IMMEDIATE_VALUE); + fsv_assert_ne(inst->src[i].file, IMM); /* A stride of 1 (the usual case) or 0, with a special * "repctrl" bit, is allowed. The repctrl bit doesn't work for diff --git a/src/intel/compiler/brw_gram.y b/src/intel/compiler/brw_gram.y index 85ef52cc2f6..a0093359bbf 100644 --- a/src/intel/compiler/brw_gram.y +++ b/src/intel/compiler/brw_gram.y @@ -670,7 +670,7 @@ unaryinstruction: $4.flag_subreg_nr); } - if ($7.file != BRW_IMMEDIATE_VALUE) { + if ($7.file != IMM) { brw_inst_set_src0_vstride(p->devinfo, brw_last_inst, $7.vstride); } @@ -881,7 +881,7 @@ sendinstruction: brw_set_src0(p, brw_last_inst, $5); brw_inst_set_bits(brw_last_inst, 127, 96, $6); brw_inst_set_src1_file_type(p->devinfo, brw_last_inst, - BRW_IMMEDIATE_VALUE, + IMM, BRW_TYPE_UD); brw_inst_set_sfid(p->devinfo, brw_last_inst, $7); brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread); @@ -912,14 +912,14 @@ sendinstruction: brw_set_src0(p, brw_last_inst, $5); brw_set_src1(p, brw_last_inst, $6); - if ($7.file == BRW_IMMEDIATE_VALUE) { + if ($7.file == IMM) { brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 0); brw_inst_set_send_desc(p->devinfo, brw_last_inst, $7.ud); } else { brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1); } - if ($8.file == BRW_IMMEDIATE_VALUE) { + if ($8.file == IMM) { brw_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 0); brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8.ud); } else { @@ -1158,7 +1158,7 @@ syncinstruction: error(&@2, "sync instruction is supported only on gfx12+\n"); } - if ($5.file == BRW_IMMEDIATE_VALUE && + if ($5.file == IMM && $3 != TGL_SYNC_ALLRD && $3 != TGL_SYNC_ALLWR) { error(&@2, "Only allrd and allwr support immediate argument\n"); @@ -1503,7 +1503,7 @@ directgenreg: GENREG subregnum { memset(&$$, '\0', sizeof($$)); - $$.file = BRW_GENERAL_REGISTER_FILE; + $$.file = FIXED_GRF; $$.nr = $1 * reg_unit(p->devinfo); $$.subnr = $2; } @@ -1513,7 +1513,7 @@ indirectgenreg: GENREGFILE LSQUARE addrparam RSQUARE { memset(&$$, '\0', sizeof($$)); - $$.file = BRW_GENERAL_REGISTER_FILE; + $$.file = FIXED_GRF; $$.subnr = $3.subnr; $$.indirect_offset = $3.indirect_offset; } @@ -1528,7 +1528,7 @@ addrreg: error(&@2, "Address sub register number %d" "out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_ADDRESS; $$.subnr = $2; } @@ -1544,7 +1544,7 @@ accreg: " out of range\n", $1); memset(&$$, '\0', sizeof($$)); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_ACCUMULATOR; $$.subnr = $2; } @@ -1564,7 +1564,7 @@ flagreg: error(&@2, "Flag subregister number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_FLAG | $1; $$.subnr = $2; } @@ -1577,7 +1577,7 @@ maskreg: error(&@1, "Mask register number %d" " out of range\n", $1); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_MASK; $$.subnr = $2; } @@ -1591,7 +1591,7 @@ notifyreg: error(&@2, "Notification sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_NOTIFICATION_COUNT; $$.subnr = $2; } @@ -1608,7 +1608,7 @@ statereg: error(&@2, "State sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_STATE; $$.subnr = $2; } @@ -1621,7 +1621,7 @@ controlreg: error(&@2, "control sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_CONTROL; $$.subnr = $2; } @@ -1642,7 +1642,7 @@ threadcontrolreg: error(&@2, "Thread control sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_TDR; $$.subnr = $2; } @@ -1661,7 +1661,7 @@ performancereg: error(&@2, "Performance sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_TIMESTAMP; $$.subnr = $2; } @@ -1674,7 +1674,7 @@ channelenablereg: error(&@1, "Channel enable register number %d" " out of range\n", $1); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.file = ARF; $$.nr = BRW_ARF_MASK; $$.subnr = $2; } diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 7a08bff01fe..758a761aca5 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -208,10 +208,10 @@ static inline uint64_t brw_reg_file_to_hw_reg_file(enum brw_reg_file file) { switch (file) { - case BRW_ARCHITECTURE_REGISTER_FILE: return 0x0; - case BRW_GENERAL_REGISTER_FILE: return 0x1; - default: /* Fallthrough. */ - case BRW_IMMEDIATE_VALUE: return 0x3; + case ARF: return 0x0; + case FIXED_GRF: return 0x1; + default: /* Fallthrough. */ + case IMM: return 0x3; } } @@ -219,9 +219,9 @@ static inline enum brw_reg_file hw_reg_file_to_brw_reg_file(uint64_t v) { switch (v) { - case 0x0: return BRW_ARCHITECTURE_REGISTER_FILE; - case 0x1: return BRW_GENERAL_REGISTER_FILE; - default: return BRW_IMMEDIATE_VALUE; + case 0x0: return ARF; + case 0x1: return FIXED_GRF; + default: return IMM; } } @@ -249,11 +249,11 @@ brw_inst_set_##name(const struct intel_device_info *devinfo, \ uint64_t value = brw_reg_file_to_hw_reg_file(file); \ if (devinfo->ver < 12) { \ if (devinfo->ver == 11 && args.grf_or_imm) { \ - assert(file == BRW_GENERAL_REGISTER_FILE || file == BRW_IMMEDIATE_VALUE); \ - value = file == BRW_GENERAL_REGISTER_FILE ? 0 : 1; \ + assert(file == FIXED_GRF || file == IMM); \ + value = file == FIXED_GRF ? 0 : 1; \ } else if (devinfo->ver == 11 && args.grf_or_acc) { \ - assert(file == BRW_GENERAL_REGISTER_FILE || file == BRW_ARCHITECTURE_REGISTER_FILE); \ - value = file == BRW_GENERAL_REGISTER_FILE ? 0 : 1; \ + assert(file == FIXED_GRF || file == ARF); \ + value = file == FIXED_GRF ? 0 : 1; \ } \ brw_inst_set_bits(inst, hi9, lo9, value); \ } else if (hi12 == lo12) { \ @@ -277,10 +277,9 @@ brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ if (devinfo->ver < 12) { \ value = brw_inst_bits(inst, hi9, lo9); \ if (devinfo->ver == 11 && args.grf_or_imm) \ - return value ? BRW_IMMEDIATE_VALUE : BRW_GENERAL_REGISTER_FILE; \ + return value ? IMM : FIXED_GRF; \ else if (devinfo->ver == 11 && args.grf_or_acc) \ - return value ? BRW_ARCHITECTURE_REGISTER_FILE \ - : BRW_GENERAL_REGISTER_FILE; \ + return value ? ARF : FIXED_GRF; \ } else if (hi12 == lo12) { \ value = brw_inst_bits(inst, hi12, lo12); \ } else { \ @@ -1052,7 +1051,7 @@ brw_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \ brw_inst *inst, enum brw_reg_file file, \ enum brw_reg_type type) \ { \ - assert(file <= BRW_IMMEDIATE_VALUE); \ + assert(file <= IMM); \ unsigned hw_type = brw_type_encode(devinfo, file, type); \ brw_inst_set_##reg##_reg_file(devinfo, inst, file); \ brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \ @@ -1063,7 +1062,7 @@ brw_inst_##reg##_type(const struct intel_device_info *devinfo, \ const brw_inst *inst) \ { \ unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \ - (unsigned) BRW_GENERAL_REGISTER_FILE : \ + (unsigned) FIXED_GRF : \ brw_inst_##reg##_reg_file(devinfo, inst); \ unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \ return brw_type_decode(devinfo, (enum brw_reg_file)file, hw_type); \ diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index b6e272c03ec..380a6ab6130 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -853,7 +853,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, brw_imm_ud(INTEL_MASK(31, 5))); } - if (sampler.file == BRW_IMMEDIATE_VALUE) { + if (sampler.file == IMM) { assert(sampler.ud >= 16); const int sampler_state_size = 16; /* 16 bytes */ @@ -2326,7 +2326,7 @@ lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld, surface_handle.file == BAD_FILE ? LSC_ADDR_SURFTYPE_BTI : LSC_ADDR_SURFTYPE_BSS; - assert(alignment_B.file == BRW_IMMEDIATE_VALUE); + assert(alignment_B.file == IMM); unsigned alignment = alignment_B.ud; inst->opcode = SHADER_OPCODE_SEND; @@ -2408,7 +2408,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) brw_reg ubo_offset = bld.vgrf(BRW_TYPE_UD); bld.MOV(ubo_offset, offset_B); - assert(inst->src[PULL_VARYING_CONSTANT_SRC_ALIGNMENT].file == BRW_IMMEDIATE_VALUE); + assert(inst->src[PULL_VARYING_CONSTANT_SRC_ALIGNMENT].file == IMM); unsigned alignment = inst->src[PULL_VARYING_CONSTANT_SRC_ALIGNMENT].ud; inst->opcode = SHADER_OPCODE_SEND; @@ -2678,17 +2678,17 @@ lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst) brw_reg globals_addr = retype(inst->src[RT_LOGICAL_SRC_GLOBALS], BRW_TYPE_UD); globals_addr.stride = 1; const brw_reg bvh_level = - inst->src[RT_LOGICAL_SRC_BVH_LEVEL].file == BRW_IMMEDIATE_VALUE ? + inst->src[RT_LOGICAL_SRC_BVH_LEVEL].file == IMM ? inst->src[RT_LOGICAL_SRC_BVH_LEVEL] : bld.move_to_vgrf(inst->src[RT_LOGICAL_SRC_BVH_LEVEL], inst->components_read(RT_LOGICAL_SRC_BVH_LEVEL)); const brw_reg trace_ray_control = - inst->src[RT_LOGICAL_SRC_TRACE_RAY_CONTROL].file == BRW_IMMEDIATE_VALUE ? + inst->src[RT_LOGICAL_SRC_TRACE_RAY_CONTROL].file == IMM ? inst->src[RT_LOGICAL_SRC_TRACE_RAY_CONTROL] : bld.move_to_vgrf(inst->src[RT_LOGICAL_SRC_TRACE_RAY_CONTROL], inst->components_read(RT_LOGICAL_SRC_TRACE_RAY_CONTROL)); const brw_reg synchronous_src = inst->src[RT_LOGICAL_SRC_SYNCHRONOUS]; - assert(synchronous_src.file == BRW_IMMEDIATE_VALUE); + assert(synchronous_src.file == IMM); const bool synchronous = synchronous_src.ud; const unsigned unit = reg_unit(devinfo); @@ -2702,8 +2702,8 @@ lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst) const unsigned ex_mlen = inst->exec_size / 8; brw_reg payload = bld.vgrf(BRW_TYPE_UD); - if (bvh_level.file == BRW_IMMEDIATE_VALUE && - trace_ray_control.file == BRW_IMMEDIATE_VALUE) { + if (bvh_level.file == IMM && + trace_ray_control.file == IMM) { uint32_t high = devinfo->ver >= 20 ? 10 : 9; bld.MOV(payload, brw_imm_ud(SET_BITS(trace_ray_control.ud, high, 8) | (bvh_level.ud & 0x7))); diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index f72be6cf950..b744d8808f3 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -228,9 +228,9 @@ static inline unsigned phys_nr(const struct intel_device_info *devinfo, const struct brw_reg reg) { if (devinfo->ver >= 20) { - if (reg.file == BRW_GENERAL_REGISTER_FILE) + if (reg.file == FIXED_GRF) return reg.nr / 2; - else if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE && + else if (reg.file == ARF && reg.nr >= BRW_ARF_ACCUMULATOR && reg.nr < BRW_ARF_FLAG) return BRW_ARF_ACCUMULATOR + (reg.nr - BRW_ARF_ACCUMULATOR) / 2; @@ -245,8 +245,8 @@ static inline unsigned phys_subnr(const struct intel_device_info *devinfo, const struct brw_reg reg) { if (devinfo->ver >= 20) { - if (reg.file == BRW_GENERAL_REGISTER_FILE || - (reg.file == BRW_ARCHITECTURE_REGISTER_FILE && + if (reg.file == FIXED_GRF || + (reg.file == ARF && reg.nr >= BRW_ARF_ACCUMULATOR && reg.nr < BRW_ARF_FLAG)) return (reg.nr & 1) * REG_SIZE + reg.subnr; @@ -380,9 +380,9 @@ brw_make_reg(enum brw_reg_file file, unsigned writemask) { struct brw_reg reg; - if (file == BRW_GENERAL_REGISTER_FILE) + if (file == FIXED_GRF) assert(nr < XE2_MAX_GRF); - else if (file == BRW_ARCHITECTURE_REGISTER_FILE) + else if (file == ARF) assert(nr <= BRW_ARF_TIMESTAMP); reg.type = type; @@ -621,7 +621,7 @@ brw_ud1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) static inline struct brw_reg brw_imm_reg(enum brw_reg_type type) { - return brw_make_reg(BRW_IMMEDIATE_VALUE, + return brw_make_reg(IMM, 0, 0, 0, @@ -766,107 +766,107 @@ brw_address(struct brw_reg reg) static inline struct brw_reg brw_vec1_grf(unsigned nr, unsigned subnr) { - return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_vec1_reg(FIXED_GRF, nr, subnr); } static inline struct brw_reg xe2_vec1_grf(unsigned nr, unsigned subnr) { - return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return brw_vec1_reg(FIXED_GRF, 2 * nr + subnr / 8, subnr % 8); } /** Construct float[2] general-purpose register */ static inline struct brw_reg brw_vec2_grf(unsigned nr, unsigned subnr) { - return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_vec2_reg(FIXED_GRF, nr, subnr); } static inline struct brw_reg xe2_vec2_grf(unsigned nr, unsigned subnr) { - return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return brw_vec2_reg(FIXED_GRF, 2 * nr + subnr / 8, subnr % 8); } /** Construct float[4] general-purpose register */ static inline struct brw_reg brw_vec4_grf(unsigned nr, unsigned subnr) { - return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_vec4_reg(FIXED_GRF, nr, subnr); } static inline struct brw_reg xe2_vec4_grf(unsigned nr, unsigned subnr) { - return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return brw_vec4_reg(FIXED_GRF, 2 * nr + subnr / 8, subnr % 8); } /** Construct float[8] general-purpose register */ static inline struct brw_reg brw_vec8_grf(unsigned nr, unsigned subnr) { - return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_vec8_reg(FIXED_GRF, nr, subnr); } static inline struct brw_reg xe2_vec8_grf(unsigned nr, unsigned subnr) { - return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return brw_vec8_reg(FIXED_GRF, 2 * nr + subnr / 8, subnr % 8); } /** Construct float[16] general-purpose register */ static inline struct brw_reg brw_vec16_grf(unsigned nr, unsigned subnr) { - return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_vec16_reg(FIXED_GRF, nr, subnr); } static inline struct brw_reg xe2_vec16_grf(unsigned nr, unsigned subnr) { - return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return brw_vec16_reg(FIXED_GRF, 2 * nr + subnr / 8, subnr % 8); } static inline struct brw_reg brw_vecn_grf(unsigned width, unsigned nr, unsigned subnr) { - return brw_vecn_reg(width, BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_vecn_reg(width, FIXED_GRF, nr, subnr); } static inline struct brw_reg xe2_vecn_grf(unsigned width, unsigned nr, unsigned subnr) { - return brw_vecn_reg(width, BRW_GENERAL_REGISTER_FILE, nr + subnr / 8, subnr % 8); + return brw_vecn_reg(width, FIXED_GRF, nr + subnr / 8, subnr % 8); } static inline struct brw_reg brw_uw1_grf(unsigned nr, unsigned subnr) { - return brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_uw1_reg(FIXED_GRF, nr, subnr); } static inline struct brw_reg brw_uw8_grf(unsigned nr, unsigned subnr) { - return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_uw8_reg(FIXED_GRF, nr, subnr); } static inline struct brw_reg brw_uw16_grf(unsigned nr, unsigned subnr) { - return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_uw16_reg(FIXED_GRF, nr, subnr); } static inline struct brw_reg brw_ud8_grf(unsigned nr, unsigned subnr) { - return brw_ud8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_ud8_reg(FIXED_GRF, nr, subnr); } static inline struct brw_reg brw_ud1_grf(unsigned nr, unsigned subnr) { - return brw_ud1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return brw_ud1_reg(FIXED_GRF, nr, subnr); } @@ -874,25 +874,25 @@ brw_ud1_grf(unsigned nr, unsigned subnr) static inline struct brw_reg brw_null_reg(void) { - return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0); + return brw_vec8_reg(ARF, BRW_ARF_NULL, 0); } static inline struct brw_reg brw_null_vec(unsigned width) { - return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0); + return brw_vecn_reg(width, ARF, BRW_ARF_NULL, 0); } static inline struct brw_reg brw_address_reg(unsigned subnr) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr); + return brw_uw1_reg(ARF, BRW_ARF_ADDRESS, subnr); } static inline struct brw_reg brw_tdr_reg(void) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_TDR, 0); + return brw_uw1_reg(ARF, BRW_ARF_TDR, 0); } /* If/else instructions break in align16 mode if writemask & swizzle @@ -902,7 +902,7 @@ brw_tdr_reg(void) static inline struct brw_reg brw_ip_reg(void) { - return brw_make_reg(BRW_ARCHITECTURE_REGISTER_FILE, + return brw_make_reg(ARF, BRW_ARF_IP, 0, 0, @@ -918,7 +918,7 @@ brw_ip_reg(void) static inline struct brw_reg brw_notification_reg(void) { - return brw_make_reg(BRW_ARCHITECTURE_REGISTER_FILE, + return brw_make_reg(ARF, BRW_ARF_NOTIFICATION_COUNT, 0, 0, @@ -934,33 +934,33 @@ brw_notification_reg(void) static inline struct brw_reg brw_cr0_reg(unsigned subnr) { - return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_CONTROL, subnr); + return brw_ud1_reg(ARF, BRW_ARF_CONTROL, subnr); } static inline struct brw_reg brw_sr0_reg(unsigned subnr) { - return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_STATE, subnr); + return brw_ud1_reg(ARF, BRW_ARF_STATE, subnr); } static inline struct brw_reg brw_acc_reg(unsigned width) { - return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE, + return brw_vecn_reg(width, ARF, BRW_ARF_ACCUMULATOR, 0); } static inline struct brw_reg brw_flag_reg(int reg, int subreg) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, + return brw_uw1_reg(ARF, BRW_ARF_FLAG + reg, subreg); } static inline struct brw_reg brw_flag_subreg(unsigned subreg) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, + return brw_uw1_reg(ARF, BRW_ARF_FLAG + subreg / 2, subreg % 2); } @@ -972,7 +972,7 @@ brw_flag_subreg(unsigned subreg) static inline struct brw_reg brw_mask_reg(unsigned subnr) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, subnr); + return brw_uw1_reg(ARF, BRW_ARF_MASK, subnr); } static inline struct brw_reg @@ -1152,7 +1152,7 @@ get_element_d(struct brw_reg reg, unsigned elt) static inline struct brw_reg brw_swizzle(struct brw_reg reg, unsigned swz) { - if (reg.file == BRW_IMMEDIATE_VALUE) + if (reg.file == IMM) reg.ud = brw_swizzle_immediate(reg.type, reg.ud, swz); else reg.swizzle = brw_compose_swizzle(swz, reg.swizzle); @@ -1163,7 +1163,7 @@ brw_swizzle(struct brw_reg reg, unsigned swz) static inline struct brw_reg brw_writemask(struct brw_reg reg, unsigned mask) { - assert(reg.file != BRW_IMMEDIATE_VALUE); + assert(reg.file != IMM); reg.writemask &= mask; return reg; } @@ -1171,7 +1171,7 @@ brw_writemask(struct brw_reg reg, unsigned mask) static inline struct brw_reg brw_set_writemask(struct brw_reg reg, unsigned mask) { - assert(reg.file != BRW_IMMEDIATE_VALUE); + assert(reg.file != IMM); reg.writemask = mask; return reg; } @@ -1247,7 +1247,7 @@ region_matches(struct brw_reg reg, enum brw_vertical_stride v, static inline unsigned element_sz(struct brw_reg reg) { - if (reg.file == BRW_IMMEDIATE_VALUE || has_scalar_region(reg)) { + if (reg.file == IMM || has_scalar_region(reg)) { return brw_type_size_bytes(reg.type); } else if (reg.width == BRW_WIDTH_1 && diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp index c260d6fce7a..c98234fa728 100644 --- a/src/intel/compiler/test_eu_compact.cpp +++ b/src/intel/compiler/test_eu_compact.cpp @@ -97,8 +97,8 @@ clear_pad_bits(const struct brw_isa_info *isa, brw_inst *inst) if (brw_inst_opcode(isa, inst) != BRW_OPCODE_SEND && brw_inst_opcode(isa, inst) != BRW_OPCODE_SENDC && - brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && - brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) { + brw_inst_src0_reg_file(devinfo, inst) != IMM && + brw_inst_src1_reg_file(devinfo, inst) != IMM) { brw_inst_set_bits(inst, 127, 111, 0); } } @@ -133,8 +133,8 @@ skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit) /* sometimes these are pad bits. */ if (brw_inst_opcode(isa, src) != BRW_OPCODE_SEND && brw_inst_opcode(isa, src) != BRW_OPCODE_SENDC && - brw_inst_src0_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE && - brw_inst_src1_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE && + brw_inst_src0_reg_file(devinfo, src) != IMM && + brw_inst_src1_reg_file(devinfo, src) != IMM && bit >= 121) { return true; } diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index 8940280b06f..156de6f1065 100644 --- a/src/intel/compiler/test_eu_validate.cpp +++ b/src/intel/compiler/test_eu_validate.cpp @@ -203,8 +203,8 @@ TEST_P(validation_test, invalid_exec_size_encoding) brw_MOV(p, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, test_case[i].exec_size); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); if (test_case[i].exec_size == BRW_EXECUTE_1) { brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); @@ -225,8 +225,8 @@ TEST_P(validation_test, invalid_exec_size_encoding) TEST_P(validation_test, invalid_type_encoding) { enum brw_reg_file files[2] = { - BRW_GENERAL_REGISTER_FILE, - BRW_IMMEDIATE_VALUE, + FIXED_GRF, + IMM, }; for (unsigned i = 0; i < ARRAY_SIZE(files); i++) { @@ -549,19 +549,19 @@ TEST_P(validation_test, 3src_inst_access_mode) TEST_P(validation_test, dest_stride_must_be_equal_to_the_ratio_of_exec_size_to_dest_size) { brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); EXPECT_FALSE(validate(p)); clear_instructions(p); brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); EXPECT_TRUE(validate(p)); } @@ -575,9 +575,9 @@ TEST_P(validation_test, dst_subreg_must_be_aligned_to_exec_type_size) brw_ADD(p, g0, g0, g0); brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 2); brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); EXPECT_FALSE(validate(p)); @@ -587,12 +587,12 @@ TEST_P(validation_test, dst_subreg_must_be_aligned_to_exec_type_size) brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4); brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 8); brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); @@ -724,8 +724,8 @@ TEST_P(validation_test, dst_horizontal_stride_0) EXPECT_FALSE(validate(p)); } -/* VertStride must be used to cross BRW_GENERAL_REGISTER_FILE register boundaries. This rule implies - * that elements within a 'Width' cannot cross BRW_GENERAL_REGISTER_FILE boundaries. +/* VertStride must be used to cross FIXED_GRF register boundaries. This rule implies + * that elements within a 'Width' cannot cross FIXED_GRF boundaries. */ TEST_P(validation_test, must_not_cross_grf_boundary_in_a_width) { @@ -824,16 +824,16 @@ TEST_P(validation_test, vstride_on_align16_must_be_0_or_4) } } -/* In Direct Addressing mode, a source cannot span more than 2 adjacent BRW_GENERAL_REGISTER_FILE +/* In Direct Addressing mode, a source cannot span more than 2 adjacent FIXED_GRF * registers. */ TEST_P(validation_test, source_cannot_span_more_than_2_registers) { brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8); brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); @@ -844,9 +844,9 @@ TEST_P(validation_test, source_cannot_span_more_than_2_registers) brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8); brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); @@ -862,15 +862,15 @@ TEST_P(validation_test, source_cannot_span_more_than_2_registers) EXPECT_TRUE(validate(p)); } -/* A destination cannot span more than 2 adjacent BRW_GENERAL_REGISTER_FILE registers. */ +/* A destination cannot span more than 2 adjacent FIXED_GRF registers. */ TEST_P(validation_test, destination_cannot_span_more_than_2_registers) { brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32); brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); EXPECT_FALSE(validate(p)); @@ -880,12 +880,12 @@ TEST_P(validation_test, destination_cannot_span_more_than_2_registers) brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_8); brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 6); brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); @@ -897,9 +897,9 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one) { /* Writes to dest are to the lower OWord */ brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); @@ -911,9 +911,9 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one) /* Writes to dest are to the upper OWord */ brw_ADD(p, g0, g0, g0); brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); @@ -925,9 +925,9 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one) /* Writes to dest are evenly split between OWords */ brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8); brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); @@ -940,12 +940,12 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one) brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4); brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 10); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2); brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); @@ -1032,9 +1032,9 @@ TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src) { brw_MOV(p, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 8); brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); @@ -1075,9 +1075,9 @@ TEST_P(validation_test, one_src_two_dst) brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); EXPECT_TRUE(validate(p)); @@ -1085,9 +1085,9 @@ TEST_P(validation_test, one_src_two_dst) brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); if (devinfo.ver >= 8) { EXPECT_TRUE(validate(p)); @@ -1099,9 +1099,9 @@ TEST_P(validation_test, one_src_two_dst) brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_D); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_D); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); if (devinfo.ver >= 8) { EXPECT_TRUE(validate(p)); @@ -1114,9 +1114,9 @@ TEST_P(validation_test, one_src_two_dst) brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1); brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); @@ -1132,12 +1132,12 @@ TEST_P(validation_test, one_src_two_dst) brw_ADD(p, g0, g0, g0); brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_dst_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); + brw_inst_set_src0_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_src1_file_type(&devinfo, last_inst, FIXED_GRF, BRW_TYPE_W); if (devinfo.ver >= 8) { EXPECT_TRUE(validate(p)); @@ -2613,7 +2613,7 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf) intel_device_info_is_9lp(&devinfo) || (devinfo.ver == 8 && inst[i].opcode == BRW_OPCODE_MUL && - brw_inst_dst_reg_file(&devinfo, last_inst) == BRW_ARCHITECTURE_REGISTER_FILE && + brw_inst_dst_reg_file(&devinfo, last_inst) == ARF && brw_inst_dst_da_reg_nr(&devinfo, last_inst) != BRW_ARF_NULL)) { EXPECT_EQ(inst[i].expected_result, validate(p)); } else {