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aco: support 32bit address in nir_load_smem_amd

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radeonsi uses 32bit address.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22525>
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Qiang Yu 2023-04-14 15:47:10 +08:00 • committed by Marge Bot
parent 3ff9153a3b
commit 31bfad83ec
1 changed files with 6 additions and 0 deletions
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6
src/amd/compiler/aco_instruction_selection.cpp
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@ -7179,6 +7179,12 @@ visit_load_smem(isel_context* ctx, nir_intrinsic_instr* instr)
Temp base = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa)); Temp base = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
Temp offset = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa)); Temp offset = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
/* If base address is 32bit, convert to 64bit with the high 32bit part. */
if (base.bytes() == 4) {
base = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
base, Operand::c32(ctx->options->address32_hi));
}
aco_opcode opcode = aco_opcode::s_load_dword; aco_opcode opcode = aco_opcode::s_load_dword;
unsigned size = 1; unsigned size = 1;