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radv/gfx9: fix tile swizzle handling for gfx9

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This sets the tile swizzle up properly for gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
David Airlie 2017-08-15 12:40:41 +10:00 • committed by Dave Airlie
parent e43cc3e3af
commit 31bb8517a1
2 changed files with 8 additions and 11 deletions
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7
src/amd/vulkan/radv_device.c
View file

@ -2983,6 +2983,7 @@ radv_initialise_color_surface(struct radv_device *device,
S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
cb->cb_color_base |= iview->image->surface.tile_swizzle;
} else {
const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
@ -3024,8 +3025,7 @@ radv_initialise_color_surface(struct radv_device *device,
va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->dcc_offset;
cb->cb_dcc_base = va >> 8;
if (device->physical_device->rad_info.chip_class < GFX9)
cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
uint32_t max_slice = radv_surface_layer_count(iview);
cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
@ -3041,8 +3041,7 @@ radv_initialise_color_surface(struct radv_device *device,
if (iview->image->fmask.size) {
va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
cb->cb_color_fmask = va >> 8;
if (device->physical_device->rad_info.chip_class < GFX9)
cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
} else {
cb->cb_color_fmask = cb->cb_color_base;
}

12
src/amd/vulkan/radv_image.c
View file

@ -215,9 +215,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
va += base_level_info->offset;
state[0] = va >> 8;
if (chip_class < GFX9)
if (base_level_info->mode == RADEON_SURF_MODE_2D)
state[0] |= image->surface.tile_swizzle;
if (chip_class >= GFX9 ||
base_level_info->mode == RADEON_SURF_MODE_2D)
state[0] |= image->surface.tile_swizzle;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
@ -230,8 +230,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va += base_level_info->dcc_offset;
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = meta_va >> 8;
if (chip_class < GFX9)
state[7] |= image->surface.tile_swizzle;
state[7] |= image->surface.tile_swizzle;
}
}
@ -479,8 +478,7 @@ si_make_texture_descriptor(struct radv_device *device,
}
fmask_state[0] = va >> 8;
if (device->physical_device->rad_info.chip_class < GFX9)
fmask_state[0] |= image->fmask.tile_swizzle;
fmask_state[0] |= image->fmask.tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT_GFX6(fmask_format) |
S_008F14_NUM_FORMAT_GFX6(num_format);