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r600/sfn: Simplify dependency chain for index loads on EG

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Address loads that just load the index register don't need to chain
up like loads if the address register that are used for indirect
register loads. With the latter it is important that the load and the
address register use are in the same clause. For index register loads
this is scheduled accordingly.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>
This commit is contained in:
Gert Wollny 2023-08-14 17:47:24 +02:00 • committed by Marge Bot
parent e9f60482fb
commit 318b838990
2 changed files with 13 additions and 15 deletions
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12
src/gallium/drivers/r600/sfn/sfn_split_address_loads.cpp
View file

@ -156,8 +156,11 @@ void AddressSplitVisitor::visit(AluInstr *instr)
if (addr) {
assert(!index);
if (!m_current_addr || !m_current_addr->equal_to(*addr))
if (!m_current_addr || !m_current_addr->equal_to(*addr)) {
load_ar(instr, addr);
for (auto na: m_prev_non_alu)
m_last_ar_load->add_required_instr(na);
}
// Do this with a visitor to catch also local array values
CollectDeps collector;
@ -205,8 +208,10 @@ auto AddressSplitVisitor::load_index_register_eg(Instr *instr,
m_last_idx_load[idx_id] = new AluInstr(idx_op[idx_id], idx, m_vf.addr(), {});
m_current_block->insert(m_block_iterator, m_last_idx_load[idx_id]);
for (auto&& i : m_last_idx_use[idx_id])
m_last_idx_load[idx_id]->add_required_instr(i);
m_last_ar_load->add_required_instr(i);
m_last_idx_use[idx_id].clear();
m_last_idx_load[idx_id]->add_required_instr(m_last_ar_load);
m_last_ar_load->inc_ar_uses();
m_last_ar_use.push_back(m_last_idx_load[idx_id]);
@ -271,9 +276,6 @@ void AddressSplitVisitor::load_ar(Instr *instr, PRegister addr)
for (auto& i : m_last_ar_use) {
m_last_ar_load->add_required_instr(i);
}
for (auto na: m_prev_non_alu) {
m_last_ar_load->add_required_instr(na);
}
m_last_ar_use.clear();
}

16
src/gallium/drivers/r600/sfn/tests/sfn_split_address_loads_test.cpp
View file

@ -504,21 +504,17 @@ OUTPUT LOC:0 NAME:1 MASK:15
SHADER
BLOCK_START
ALU_GROUP_BEGIN
ALU MOV S0.x@free : KC0[1].x {W}
ALU MOV S0.y@free : KC0[1].y {WL}
ALU_GROUP_END
BLOCK_END
BLOCK_START
TEX SAMPLE S3.xyzw : S0.xy__ RID:0 SID:0 NNNN
BLOCK_END
BLOCK_START
ALU_GROUP_BEGIN
ALU MOVA_INT AR : KC0[0].x {L}
ALU MOVA_INT AR : KC0[0].x {}
ALU MOV S0.y@free : KC0[1].y {W}
ALU MOV S0.z@free : KC0[1].x {WL}
ALU_GROUP_END
ALU_GROUP_BEGIN
ALU SET_CF_IDX0 IDX0 : AR {L}
ALU_GROUP_END
BLOCK_END
BLOCK_START
TEX SAMPLE S3.xyzw : S0.zy__ RID:0 SID:0 NNNN
BLOCK_END
BLOCK_START
ALU_GROUP_BEGIN
ALU ADD S4.x@chgr : KC1[IDX0][0].x S3.x {W}