diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 2428ba6cdc4..6821ed08ce9 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -736,8 +736,6 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, return 16; case PIPE_SHADER_CAP_SUPPORTED_IRS: return (1 << PIPE_SHADER_IR_NIR) | - COND(has_compute(screen) && (shader == PIPE_SHADER_COMPUTE), - (1 << PIPE_SHADER_IR_NIR_SERIALIZED)) | /* tgsi_to_nir doesn't support all stages: */ COND((shader == PIPE_SHADER_VERTEX) || (shader == PIPE_SHADER_FRAGMENT) || diff --git a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c index d4026a419ff..a0fdd1c62ff 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c @@ -292,16 +292,6 @@ ir3_shader_compute_state_create(struct pipe_context *pctx, if (cso->ir_type == PIPE_SHADER_IR_NIR) { /* we take ownership of the reference: */ nir = (nir_shader *)cso->prog; - } else if (cso->ir_type == PIPE_SHADER_IR_NIR_SERIALIZED) { - const nir_shader_compiler_options *options = - ir3_get_compiler_options(compiler); - const struct pipe_binary_program_header *hdr = cso->prog; - struct blob_reader reader; - - blob_reader_init(&reader, hdr->blob, hdr->num_bytes); - nir = nir_deserialize(NULL, options, &reader); - - ir3_finalize_nir(compiler, &ir3_options.nir_options, nir); } else { assert(cso->ir_type == PIPE_SHADER_IR_TGSI); if (ir3_shader_debug & IR3_DBG_DISASM) { diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 320524f144b..790f4c6ea8c 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -3235,9 +3235,6 @@ iris_create_compute_state(struct pipe_context *ctx, struct iris_context *ice = (void *) ctx; struct iris_screen *screen = (void *) ctx->screen; struct u_upload_mgr *uploader = ice->shaders.uploader_unsync; - const nir_shader_compiler_options *options = - screen->brw ? screen->brw->nir_options[MESA_SHADER_COMPUTE] - : screen->elk->nir_options[MESA_SHADER_COMPUTE]; nir_shader *nir; switch (state->ir_type) { @@ -3245,14 +3242,6 @@ iris_create_compute_state(struct pipe_context *ctx, nir = (void *)state->prog; break; - case PIPE_SHADER_IR_NIR_SERIALIZED: { - struct blob_reader reader; - const struct pipe_binary_program_header *hdr = state->prog; - blob_reader_init(&reader, hdr->blob, hdr->num_bytes); - nir = nir_deserialize(NULL, options, &reader); - break; - } - default: unreachable("Unsupported IR"); } diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index ed5a02b9232..fbc4095a3d0 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -116,15 +116,6 @@ iris_get_driver_uuid(struct pipe_screen *pscreen, char *uuid) intel_uuid_compute_driver_id((uint8_t *)uuid, devinfo, PIPE_UUID_SIZE); } -static bool -iris_enable_clover() -{ - static int enable = -1; - if (enable < 0) - enable = debug_get_bool_option("IRIS_ENABLE_CLOVER", false); - return enable; -} - static void iris_warn_cl() { @@ -551,12 +542,8 @@ iris_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; - case PIPE_SHADER_CAP_SUPPORTED_IRS: { - int irs = 1 << PIPE_SHADER_IR_NIR; - if (iris_enable_clover()) - irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED; - return irs; - } + case PIPE_SHADER_CAP_SUPPORTED_IRS: + return 1 << PIPE_SHADER_IR_NIR; case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 0; diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index f85911b4703..aeb2b938dd4 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -408,8 +408,7 @@ llvmpipe_get_shader_param(struct pipe_screen *screen, case PIPE_SHADER_COMPUTE: if ((lscreen->allow_cl) && param == PIPE_SHADER_CAP_SUPPORTED_IRS) return ((1 << PIPE_SHADER_IR_TGSI) | - (1 << PIPE_SHADER_IR_NIR) | - (1 << PIPE_SHADER_IR_NIR_SERIALIZED)); + (1 << PIPE_SHADER_IR_NIR)); FALLTHROUGH; case PIPE_SHADER_MESH: case PIPE_SHADER_TASK: diff --git a/src/gallium/drivers/llvmpipe/lp_state_cs.c b/src/gallium/drivers/llvmpipe/lp_state_cs.c index 581b7638fa7..15ed604216d 100644 --- a/src/gallium/drivers/llvmpipe/lp_state_cs.c +++ b/src/gallium/drivers/llvmpipe/lp_state_cs.c @@ -934,14 +934,6 @@ llvmpipe_create_compute_state(struct pipe_context *pipe, if (templ->ir_type == PIPE_SHADER_IR_TGSI) { shader->base.ir.nir = tgsi_to_nir(templ->prog, pipe->screen, false); - } else if (templ->ir_type == PIPE_SHADER_IR_NIR_SERIALIZED) { - struct blob_reader reader; - const struct pipe_binary_program_header *hdr = templ->prog; - - blob_reader_init(&reader, hdr->blob, hdr->num_bytes); - shader->base.ir.nir = nir_deserialize(NULL, pipe->screen->get_compiler_options(pipe->screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE), &reader); - - pipe->screen->finalize_nir(pipe->screen, shader->base.ir.nir); } else if (templ->ir_type == PIPE_SHADER_IR_NIR) { shader->base.ir.nir = (struct nir_shader *)templ->prog; } diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c b/src/gallium/drivers/nouveau/nouveau_screen.c index be5934c92ed..3d6defb4098 100644 --- a/src/gallium/drivers/nouveau/nouveau_screen.c +++ b/src/gallium/drivers/nouveau/nouveau_screen.c @@ -309,7 +309,6 @@ nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev) if (nv_dbg) nouveau_mesa_debug = atoi(nv_dbg); - screen->force_enable_cl = debug_get_bool_option("NOUVEAU_ENABLE_CL", false); screen->disable_fences = debug_get_bool_option("NOUVEAU_DISABLE_FENCES", false); /* These must be set before any failure is possible, as the cleanup diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h b/src/gallium/drivers/nouveau/nouveau_screen.h index ab16eae72e1..43e43bb2f3f 100644 --- a/src/gallium/drivers/nouveau/nouveau_screen.h +++ b/src/gallium/drivers/nouveau/nouveau_screen.h @@ -65,7 +65,6 @@ struct nouveau_screen { struct disk_cache *disk_shader_cache; - bool force_enable_cl; bool has_svm; bool is_uma; bool disable_fences; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 62ae898f30e..00c44f7acc4 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -393,12 +393,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, } switch (param) { - case PIPE_SHADER_CAP_SUPPORTED_IRS: { - uint32_t irs = 1 << PIPE_SHADER_IR_NIR; - if (screen->force_enable_cl) - irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED; - return irs; - } + case PIPE_SHADER_CAP_SUPPORTED_IRS: + return 1 << PIPE_SHADER_IR_NIR; case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c index c7a22742fee..b7f6d6f1d28 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c @@ -748,14 +748,6 @@ nvc0_cp_state_create(struct pipe_context *pipe, case PIPE_SHADER_IR_NIR: prog->nir = (nir_shader *)cso->prog; break; - case PIPE_SHADER_IR_NIR_SERIALIZED: { - struct blob_reader reader; - const struct pipe_binary_program_header *hdr = cso->prog; - - blob_reader_init(&reader, hdr->blob, hdr->num_bytes); - prog->nir = nir_deserialize(NULL, pipe->screen->get_compiler_options(pipe->screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE), &reader); - break; - } default: assert(!"unsupported IR!"); free(prog); diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index 0f9e5f886a4..2bca75f2731 100644 --- a/src/gallium/include/pipe/p_defines.h +++ b/src/gallium/include/pipe/p_defines.h @@ -1110,7 +1110,6 @@ enum pipe_shader_ir PIPE_SHADER_IR_TGSI = 0, PIPE_SHADER_IR_NATIVE, PIPE_SHADER_IR_NIR, - PIPE_SHADER_IR_NIR_SERIALIZED, }; /**