mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 07:28:11 +02:00
r600 : Initial version of glsl fc.
This commit is contained in:
Richard Li
parent
fafc016e1f
commit
3132853e12
7 changed files with 2189 additions and 84 deletions
File diff suppressed because it is too large
Load diff
|
|
@ -72,7 +72,8 @@ typedef enum SrcRegisterType
|
|||
SRC_REG_INPUT = 1,
|
||||
SRC_REG_CONSTANT = 2,
|
||||
SRC_REG_ALT_TEMPORARY = 3,
|
||||
NUMBER_OF_SRC_REG_TYPE = 4
|
||||
SRC_REC_LITERAL = 4,
|
||||
NUMBER_OF_SRC_REG_TYPE = 5
|
||||
} SrcRegisterType;
|
||||
|
||||
typedef enum DstRegisterType
|
||||
|
|
@ -111,6 +112,12 @@ typedef struct PVSDSTtag
|
|||
BITS addrmode1:1; //32
|
||||
} PVSDST;
|
||||
|
||||
typedef struct PVSINSTtag
|
||||
{
|
||||
BITS literal :2;
|
||||
BITS SaturateMode :2;
|
||||
} PVSINST;
|
||||
|
||||
typedef struct PVSSRCtag
|
||||
{
|
||||
BITS rtype:4;
|
||||
|
|
@ -148,6 +155,7 @@ typedef union PVSDWORDtag
|
|||
{
|
||||
BITS bits;
|
||||
PVSDST dst;
|
||||
PVSINST dst2;
|
||||
PVSSRC src;
|
||||
PVSMATH math;
|
||||
float f;
|
||||
|
|
@ -263,14 +271,15 @@ enum
|
|||
|
||||
typedef struct FC_LEVEL
|
||||
{
|
||||
unsigned int first; ///< first fc instruction on level (if, rep, loop)
|
||||
unsigned int* mid; ///< middle instructions - else or all breaks on this level
|
||||
unsigned int midLen;
|
||||
unsigned int type;
|
||||
unsigned int cond;
|
||||
unsigned int inv;
|
||||
unsigned int bpush; ///< 1 if first instruction does branch stack push
|
||||
int id; ///< id of bool or int variable
|
||||
R700ControlFlowGenericClause * first;
|
||||
R700ControlFlowGenericClause ** mid;
|
||||
unsigned int unNumMid;
|
||||
unsigned int midLen;
|
||||
unsigned int type;
|
||||
unsigned int cond;
|
||||
unsigned int inv;
|
||||
unsigned int bpush; ///< 1 if first instruction does branch stack push
|
||||
int id; ///< id of bool or int variable
|
||||
} FC_LEVEL;
|
||||
|
||||
typedef struct VTX_FETCH_METHOD
|
||||
|
|
@ -279,6 +288,28 @@ typedef struct VTX_FETCH_METHOD
|
|||
GLuint mega_fetch_remainder;
|
||||
} VTX_FETCH_METHOD;
|
||||
|
||||
typedef struct SUB_OFFSET
|
||||
{
|
||||
GLint subIL_Offset;
|
||||
GLuint unCFoffset;
|
||||
TypedShaderList lstCFInstructions_local;
|
||||
} SUB_OFFSET;
|
||||
|
||||
typedef struct CALLER_POINTER
|
||||
{
|
||||
GLint subIL_Offset;
|
||||
GLint subDescIndex;
|
||||
R700ControlFlowGenericClause* cf_ptr;
|
||||
} CALLER_POINTER;
|
||||
|
||||
#define SQ_MAX_CALL_DEPTH 0x00000020
|
||||
|
||||
typedef struct CALL_LEVEL
|
||||
{
|
||||
unsigned int FCSP_BeforeEntry;
|
||||
TypedShaderList * plstCFInstructions_local;
|
||||
} CALL_LEVEL;
|
||||
|
||||
typedef struct r700_AssemblerBase
|
||||
{
|
||||
R700ControlFlowSXClause* cf_last_export_ptr;
|
||||
|
|
@ -294,11 +325,14 @@ typedef struct r700_AssemblerBase
|
|||
// No clause has been created yet
|
||||
CF_CLAUSE_TYPE cf_current_clause_type;
|
||||
|
||||
BITS alu_x_opcode;
|
||||
|
||||
GLuint number_of_exports;
|
||||
GLuint number_of_colorandz_exports;
|
||||
GLuint number_of_export_opcodes;
|
||||
|
||||
PVSDWORD D;
|
||||
PVSDWORD D2;
|
||||
PVSDWORD S[3];
|
||||
|
||||
unsigned int uLastPosUpdate;
|
||||
|
|
@ -310,6 +344,8 @@ typedef struct r700_AssemblerBase
|
|||
unsigned int number_used_registers;
|
||||
unsigned int uUsedConsts;
|
||||
|
||||
unsigned int flag_reg_index;
|
||||
|
||||
// Fragment programs
|
||||
unsigned int uiFP_AttributeMap[FRAG_ATTRIB_MAX];
|
||||
unsigned int uiFP_OutputMap[FRAG_RESULT_MAX];
|
||||
|
|
@ -378,6 +414,18 @@ typedef struct r700_AssemblerBase
|
|||
GLboolean is_tex;
|
||||
/* we inserted helper intructions and need barrier on next TEX ins */
|
||||
GLboolean need_tex_barrier;
|
||||
|
||||
SUB_OFFSET * subs;
|
||||
GLuint unSubArraySize;
|
||||
GLuint unSubArrayPointer;
|
||||
CALLER_POINTER * callers;
|
||||
GLuint unCallerArraySize;
|
||||
GLuint unCallerArrayPointer;
|
||||
unsigned int CALLSP;
|
||||
CALL_LEVEL CALLSTACK[SQ_MAX_CALL_DEPTH];
|
||||
|
||||
GLuint unCFflags;
|
||||
|
||||
} r700_AssemblerBase;
|
||||
|
||||
//Internal use
|
||||
|
|
@ -446,6 +494,10 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr,
|
|||
GLboolean add_alu_instruction(r700_AssemblerBase* pAsm,
|
||||
R700ALUInstruction* alu_instruction_ptr,
|
||||
GLuint contiguous_slots_needed);
|
||||
|
||||
GLboolean add_cf_instruction(r700_AssemblerBase* pAsm);
|
||||
void add_return_inst(r700_AssemblerBase *pAsm);
|
||||
|
||||
void get_src_properties(R700ALUInstruction* alu_instruction_ptr,
|
||||
int source_index,
|
||||
BITS* psrc_sel,
|
||||
|
|
@ -467,6 +519,21 @@ GLboolean check_vector(r700_AssemblerBase* pAsm,
|
|||
R700ALUInstruction* alu_instruction_ptr);
|
||||
GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm);
|
||||
GLboolean next_ins(r700_AssemblerBase *pAsm);
|
||||
|
||||
GLboolean next_ins2(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_alu_instruction2(r700_AssemblerBase *pAsm);
|
||||
|
||||
/* TODO : merge next_ins/2/literal, assemble_alu_instruction/2/literal */
|
||||
GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral);
|
||||
GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral);
|
||||
|
||||
GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops);
|
||||
GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset);
|
||||
GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue);
|
||||
GLboolean testFlag(r700_AssemblerBase *pAsm);
|
||||
GLboolean breakLoopOnFlag(r700_AssemblerBase *pAsm, GLuint unFCSP);
|
||||
GLboolean returnOnFlag(r700_AssemblerBase *pAsm);
|
||||
|
||||
GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode);
|
||||
GLboolean assemble_ABS(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_ADD(r700_AssemblerBase *pAsm);
|
||||
|
|
@ -497,14 +564,32 @@ GLboolean assemble_RSQ(r700_AssemblerBase *pAsm);
|
|||
GLboolean assemble_SIN(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_SCS(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_SGE(r700_AssemblerBase *pAsm);
|
||||
|
||||
GLboolean assemble_LOGIC(r700_AssemblerBase *pAsm, BITS opcode);
|
||||
GLboolean assemble_LOGIC_PRED(r700_AssemblerBase *pAsm, BITS opcode);
|
||||
|
||||
GLboolean assemble_SLT(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_STP(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_TEX(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_XPD(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_IF(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse);
|
||||
GLboolean assemble_ELSE(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm);
|
||||
|
||||
GLboolean assemble_BGNLOOP(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_BRK(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_COND(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_ENDLOOP(r700_AssemblerBase *pAsm);
|
||||
|
||||
GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex);
|
||||
GLboolean assemble_ENDSUB(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_RET(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_CAL(r700_AssemblerBase *pAsm,
|
||||
GLint nILindex,
|
||||
GLuint uiNumberInsts,
|
||||
struct prog_instruction *pILInst);
|
||||
|
||||
GLboolean Process_Export(r700_AssemblerBase* pAsm,
|
||||
GLuint type,
|
||||
GLuint export_starting_index,
|
||||
|
|
@ -516,12 +601,16 @@ GLboolean Move_Depth_Exports_To_Correct_Channels(r700_AssemblerBase *pAsm,
|
|||
|
||||
|
||||
//Interface
|
||||
GLboolean AssembleInstr(GLuint uiNumberInsts,
|
||||
GLboolean AssembleInstr(GLuint uiFirstInst,
|
||||
GLuint uiNumberInsts,
|
||||
struct prog_instruction *pILInst,
|
||||
r700_AssemblerBase *pR700AsmCode);
|
||||
GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten);
|
||||
GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten);
|
||||
|
||||
GLboolean RelocProgram(r700_AssemblerBase * pAsm);
|
||||
GLboolean InitShaderProgram(r700_AssemblerBase * pAsm);
|
||||
|
||||
int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700_Shader* pShader);
|
||||
GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode);
|
||||
|
||||
|
|
|
|||
|
|
@ -442,68 +442,77 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *
|
|||
|
||||
static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
|
||||
{
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
|
||||
struct radeon_bo * pbo;
|
||||
BATCH_LOCALS(&context->radeon);
|
||||
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
|
||||
struct radeon_bo * pbo;
|
||||
BATCH_LOCALS(&context->radeon);
|
||||
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
|
||||
|
||||
pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
|
||||
pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
|
||||
|
||||
if (!pbo)
|
||||
return;
|
||||
if (!pbo)
|
||||
return;
|
||||
|
||||
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
|
||||
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
|
||||
|
||||
BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
|
||||
R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
|
||||
R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
|
||||
R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
|
||||
pbo,
|
||||
r700->ps.SQ_PGM_START_PS.u32All,
|
||||
RADEON_GEM_DOMAIN_GTT, 0, 0);
|
||||
END_BATCH();
|
||||
BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
|
||||
R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
|
||||
R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
|
||||
R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
|
||||
pbo,
|
||||
r700->ps.SQ_PGM_START_PS.u32All,
|
||||
RADEON_GEM_DOMAIN_GTT, 0, 0);
|
||||
END_BATCH();
|
||||
|
||||
BEGIN_BATCH_NO_AUTOSTATE(9);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
|
||||
END_BATCH();
|
||||
BEGIN_BATCH_NO_AUTOSTATE(9);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
|
||||
END_BATCH();
|
||||
|
||||
COMMIT_BATCH();
|
||||
BEGIN_BATCH_NO_AUTOSTATE(3);
|
||||
R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
|
||||
END_BATCH();
|
||||
|
||||
COMMIT_BATCH();
|
||||
|
||||
}
|
||||
|
||||
static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
|
||||
{
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
|
||||
struct radeon_bo * pbo;
|
||||
BATCH_LOCALS(&context->radeon);
|
||||
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
|
||||
struct radeon_bo * pbo;
|
||||
BATCH_LOCALS(&context->radeon);
|
||||
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
|
||||
|
||||
pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
|
||||
pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
|
||||
|
||||
if (!pbo)
|
||||
return;
|
||||
if (!pbo)
|
||||
return;
|
||||
|
||||
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
|
||||
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
|
||||
|
||||
BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
|
||||
R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
|
||||
R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
|
||||
R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
|
||||
pbo,
|
||||
r700->vs.SQ_PGM_START_VS.u32All,
|
||||
RADEON_GEM_DOMAIN_GTT, 0, 0);
|
||||
END_BATCH();
|
||||
BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
|
||||
R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
|
||||
R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
|
||||
R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
|
||||
pbo,
|
||||
r700->vs.SQ_PGM_START_VS.u32All,
|
||||
RADEON_GEM_DOMAIN_GTT, 0, 0);
|
||||
END_BATCH();
|
||||
|
||||
BEGIN_BATCH_NO_AUTOSTATE(6);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
|
||||
END_BATCH();
|
||||
BEGIN_BATCH_NO_AUTOSTATE(6);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
|
||||
R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
|
||||
END_BATCH();
|
||||
|
||||
COMMIT_BATCH();
|
||||
BEGIN_BATCH_NO_AUTOSTATE(3);
|
||||
R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F);
|
||||
//R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
|
||||
END_BATCH();
|
||||
|
||||
COMMIT_BATCH();
|
||||
}
|
||||
|
||||
static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
|
||||
|
|
|
|||
|
|
@ -73,11 +73,11 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm,
|
|||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++;
|
||||
}
|
||||
|
||||
unBit = 1 << FRAG_ATTRIB_FOGC;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++;
|
||||
}
|
||||
unBit = 1 << FRAG_ATTRIB_FOGC;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++;
|
||||
}
|
||||
|
||||
for(i=0; i<8; i++)
|
||||
{
|
||||
|
|
@ -88,6 +88,62 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm,
|
|||
}
|
||||
}
|
||||
|
||||
/* order has been taken care of */
|
||||
#if 1
|
||||
for(i=FRAG_ATTRIB_VAR0; i<FRAG_ATTRIB_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers++;
|
||||
}
|
||||
}
|
||||
#else
|
||||
if( (mesa_fp->Base.InputsRead >> FRAG_ATTRIB_VAR0) > 0 )
|
||||
{
|
||||
struct r700_vertex_program_cont *vpc =
|
||||
(struct r700_vertex_program_cont *)ctx->VertexProgram._Current;
|
||||
struct gl_program_parameter_list * VsVarying = vpc->mesa_program.Base.Varying;
|
||||
struct gl_program_parameter_list * PsVarying = mesa_fp->Base.Varying;
|
||||
struct gl_program_parameter * pVsParam;
|
||||
struct gl_program_parameter * pPsParam;
|
||||
GLuint j, k;
|
||||
GLuint unMaxVarying = 0;
|
||||
|
||||
for(i=0; i<VsVarying->NumParameters; i++)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[i + FRAG_ATTRIB_VAR0] = 0;
|
||||
}
|
||||
|
||||
for(i=FRAG_ATTRIB_VAR0; i<FRAG_ATTRIB_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
j = i - FRAG_ATTRIB_VAR0;
|
||||
pPsParam = PsVarying->Parameters + j;
|
||||
|
||||
for(k=0; k<VsVarying->NumParameters; k++)
|
||||
{
|
||||
pVsParam = VsVarying->Parameters + k;
|
||||
|
||||
if( strcmp(pPsParam->Name, pVsParam->Name) == 0)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers + k;
|
||||
if(k > unMaxVarying)
|
||||
{
|
||||
unMaxVarying = k;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pAsm->number_used_registers += unMaxVarying + 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Map temporary registers (GPRs) */
|
||||
pAsm->starting_temp_register_number = pAsm->number_used_registers;
|
||||
|
||||
|
|
@ -127,6 +183,8 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm,
|
|||
pAsm->pucOutMask[ui] = 0x0;
|
||||
}
|
||||
|
||||
pAsm->flag_reg_index = pAsm->number_used_registers++;
|
||||
|
||||
pAsm->uFirstHelpReg = pAsm->number_used_registers;
|
||||
}
|
||||
|
||||
|
|
@ -247,8 +305,11 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp,
|
|||
{
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
InitShaderProgram(&(fp->r700AsmCode));
|
||||
|
||||
if( GL_FALSE == AssembleInstr(mesa_fp->Base.NumInstructions,
|
||||
if( GL_FALSE == AssembleInstr(0,
|
||||
mesa_fp->Base.NumInstructions,
|
||||
&(mesa_fp->Base.Instructions[0]),
|
||||
&(fp->r700AsmCode)) )
|
||||
{
|
||||
|
|
@ -260,6 +321,11 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp,
|
|||
return GL_FALSE;
|
||||
}
|
||||
|
||||
if( GL_FALSE == RelocProgram(&(fp->r700AsmCode)) )
|
||||
{
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
fp->r700Shader.nRegs = (fp->r700AsmCode.number_used_registers == 0) ? 0
|
||||
: (fp->r700AsmCode.number_used_registers - 1);
|
||||
|
||||
|
|
@ -459,6 +525,22 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
|
|||
}
|
||||
}
|
||||
|
||||
for(i=FRAG_ATTRIB_VAR0; i<FRAG_ATTRIB_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
ui = pAsm->uiFP_AttributeMap[i];
|
||||
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
|
||||
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
|
||||
SEMANTIC_shift, SEMANTIC_mask);
|
||||
if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
|
||||
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
else
|
||||
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
}
|
||||
}
|
||||
|
||||
exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
|
||||
if (r700->CB_SHADER_CONTROL.u32All != ((1 << exportCount) - 1))
|
||||
{
|
||||
|
|
|
|||
|
|
@ -159,13 +159,18 @@ void Init_R700_Shader(R700_Shader * pShader)
|
|||
pShader->lstVTXInstructions.uNumOfNode=0;
|
||||
}
|
||||
|
||||
void SetActiveCFlist(R700_Shader *pShader, TypedShaderList * plstCF)
|
||||
{
|
||||
pShader->plstCFInstructions_active = plstCF;
|
||||
}
|
||||
|
||||
void AddCFInstruction(R700_Shader *pShader, R700ControlFlowInstruction *pCFInst)
|
||||
{
|
||||
R700ControlFlowSXClause* pSXClause;
|
||||
R700ControlFlowSMXClause* pSMXClause;
|
||||
|
||||
pCFInst->m_uIndex = pShader->lstCFInstructions.uNumOfNode;
|
||||
AddInstToList(&(pShader->lstCFInstructions),
|
||||
pCFInst->m_uIndex = pShader->plstCFInstructions_active->uNumOfNode;
|
||||
AddInstToList(pShader->plstCFInstructions_active,
|
||||
(R700ShaderInstruction*)pCFInst);
|
||||
pShader->uShaderBinaryDWORDSize += GetInstructionSize(pCFInst->m_ShaderInstType);
|
||||
|
||||
|
|
|
|||
|
|
@ -109,6 +109,7 @@ typedef struct R700_Shader
|
|||
GLuint uStackSize;
|
||||
GLuint uMaxCallDepth;
|
||||
|
||||
TypedShaderList * plstCFInstructions_active;
|
||||
TypedShaderList lstCFInstructions;
|
||||
TypedShaderList lstALUInstructions;
|
||||
TypedShaderList lstTEXInstructions;
|
||||
|
|
@ -132,13 +133,13 @@ void TakeInstOutFromList(TypedShaderList * plstCFInstructions, R700ShaderInstruc
|
|||
void ResolveLinks(R700_Shader *pShader);
|
||||
void Assemble(R700_Shader *pShader);
|
||||
|
||||
|
||||
//Interface
|
||||
void Init_R700_Shader(R700_Shader * pShader);
|
||||
void AddCFInstruction(R700_Shader *pShader, R700ControlFlowInstruction *pCFInst);
|
||||
void AddVTXInstruction(R700_Shader *pShader, R700VertexInstruction *pVTXInst);
|
||||
void AddTEXInstruction(R700_Shader *pShader, R700TextureInstruction *pTEXInst);
|
||||
void AddALUInstruction(R700_Shader *pShader, R700ALUInstruction *pALUInst);
|
||||
void SetActiveCFlist(R700_Shader *pShader, TypedShaderList * plstCF);
|
||||
|
||||
void LoadProgram(R700_Shader *pShader);
|
||||
void UpdateShaderRegisters(R700_Shader *pShader);
|
||||
|
|
|
|||
|
|
@ -111,6 +111,15 @@ unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm,
|
|||
}
|
||||
}
|
||||
|
||||
for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[i] = unTotal++;
|
||||
}
|
||||
}
|
||||
|
||||
return (unTotal - unStart);
|
||||
}
|
||||
|
||||
|
|
@ -235,6 +244,8 @@ void Map_Vertex_Program(GLcontext *ctx,
|
|||
pAsm->number_used_registers += mesa_vp->Base.NumTemporaries;
|
||||
}
|
||||
|
||||
pAsm->flag_reg_index = pAsm->number_used_registers++;
|
||||
|
||||
pAsm->uFirstHelpReg = pAsm->number_used_registers;
|
||||
}
|
||||
|
||||
|
|
@ -324,7 +335,10 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
if(GL_FALSE == AssembleInstr(vp->mesa_program->Base.NumInstructions,
|
||||
InitShaderProgram(&(vp->r700AsmCode));
|
||||
|
||||
if(GL_FALSE == AssembleInstr(0,
|
||||
vp->mesa_program->Base.NumInstructions,
|
||||
&(vp->mesa_program->Base.Instructions[0]),
|
||||
&(vp->r700AsmCode)) )
|
||||
{
|
||||
|
|
@ -336,6 +350,11 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
if( GL_FALSE == RelocProgram(&(vp->r700AsmCode)) )
|
||||
{
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0
|
||||
: (vp->r700AsmCode.number_used_registers - 1);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue