fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 09:08:10 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

iris: Drop some workarounds which are no longer necessary

Browse source 
These workarounds are no longer required by 10th Gen hardware.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495>
This commit is contained in:
Kenneth Graunke 2020-01-16 16:34:10 -08:00
parent d1166a3b3a
commit 311cab27e2
1 changed files with 1 additions and 36 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

37
src/gallium/drivers/iris/iris_state.c
View file

@ -779,7 +779,7 @@ iris_emit_default_l3_config(struct iris_batch *batch,
iris_emit_l3_config(batch, cfg, has_slm, wants_dc_cache);
}
#if GEN_GEN == 9 || GEN_GEN == 10
#if GEN_GEN == 9
static void
iris_enable_obj_preemption(struct iris_batch *batch, bool enable)
{
@ -1015,11 +1015,6 @@ iris_init_render_context(struct iris_batch *batch)
iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo);
iris_alloc_push_constants(batch);
#if GEN_GEN == 10
/* Gen11+ is enabled for us by the kernel. */
iris_enable_obj_preemption(batch, true);
#endif
}
static void
@ -6858,17 +6853,6 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
PIPE_CONTROL_CS_STALL, bo, offset, imm);
}
if (GEN_GEN == 10 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
/* Cannonlake:
* "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
* another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
* = 0 and Pipe Control Flush Enable (bit 7) = 1"
*/
iris_emit_raw_pipe_control(batch,
"workaround: PC flush before RT flush",
PIPE_CONTROL_FLUSH_ENABLE, bo, offset, imm);
}
/* "Flush Types" workarounds ---------------------------------------------
* We do these now because they may add post-sync operations or CS stalls.
*/
@ -6887,25 +6871,6 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
}
}
/* #1130 from Gen10 workarounds page:
*
* "Enable Depth Stall on every Post Sync Op if Render target Cache
* Flush is not enabled in same PIPE CONTROL and Enable Pixel score
* board stall if Render target cache flush is enabled."
*
* Applicable to CNL B0 and C0 steppings only.
*
* The wording here is unclear, and this workaround doesn't look anything
* like the internal bug report recommendations, but leave it be for now...
*/
if (GEN_GEN == 10) {
if (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) {
flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
} else if (flags & non_lri_post_sync_flags) {
flags |= PIPE_CONTROL_DEPTH_STALL;
}
}
if (flags & PIPE_CONTROL_DEPTH_STALL) {
/* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
*