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nak: Replace Src::new_zero() with a ZERO constant

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Constants have different rules with respect to the Copy trait and using
a constant will allow us to initialize arrays even once Copy is gone.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34794>
This commit is contained in:
Faith Ekstrand 2025-05-05 18:05:43 -04:00 • committed by Marge Bot
parent f21557154b
commit 30f6ca6391
7 changed files with 27 additions and 29 deletions
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10
src/nouveau/compiler/nak/from_nir.rs
View file

@ -592,7 +592,7 @@ impl<'a> ShaderFromNir<'a> {
}
let psrc = {
let mut res = [Src::new_zero(); 4];
let mut res = [Src::ZERO; 4];
for (idx, src) in psrc.iter().enumerate() {
if let Some(src) = src {
@ -608,7 +608,7 @@ impl<'a> ShaderFromNir<'a> {
}
16 => {
for dc in 0..bits.div_ceil(32) {
let mut psrc = [Src::new_zero(); 2];
let mut psrc = [Src::ZERO; 2];
let mut psel = [0_u8; 4];
for w in 0..2 {
@ -660,7 +660,7 @@ impl<'a> ShaderFromNir<'a> {
}
}
let mut prmt_srcs = [Src::new_zero(); 4];
let mut prmt_srcs = [Src::ZERO; 4];
let mut prmt = [0_u8; 4];
for b in 0..num_bytes {
for (ds, s) in prmt_srcs.iter_mut().enumerate() {
@ -886,9 +886,9 @@ impl<'a> ShaderFromNir<'a> {
}
nir_op_fabs | nir_op_fadd | nir_op_fneg => {
let (x, y) = match alu.op {
nir_op_fabs => (Src::new_zero().fneg(), srcs(0).fabs()),
nir_op_fabs => (Src::ZERO.fneg(), srcs(0).fabs()),
nir_op_fadd => (srcs(0), srcs(1)),
nir_op_fneg => (Src::new_zero().fneg(), srcs(0).fneg()),
nir_op_fneg => (Src::ZERO.fneg(), srcs(0).fneg()),
_ => panic!("Unhandled case"),
};
let ftype = FloatType::from_bits(alu.def.bit_size().into());

8
src/nouveau/compiler/nak/ir.rs
View file

@ -1111,9 +1111,11 @@ pub struct Src {
}
impl Src {
pub fn new_zero() -> Src {
SrcRef::Zero.into()
}
pub const ZERO: Src = Src {
src_ref: SrcRef::Zero,
src_mod: SrcMod::None,
src_swizzle: SrcSwizzle::None,
};
pub fn new_imm_u32(u: u32) -> Src {
u.into()

10
src/nouveau/compiler/nak/legalize.rs
View file

@ -239,7 +239,7 @@ pub trait LegalizeBuildHelpers: SSABuilder {
let val = self.alloc_ssa(reg_file);
self.push_op(OpHAdd2 {
dst: val.into(),
srcs: [Src::new_zero().fneg(), *src],
srcs: [Src::ZERO.fneg(), *src],
saturate: false,
ftz: false,
f32: false,
@ -250,7 +250,7 @@ pub trait LegalizeBuildHelpers: SSABuilder {
let val = self.alloc_ssa(reg_file);
self.push_op(OpFAdd {
dst: val.into(),
srcs: [Src::new_zero().fneg(), *src],
srcs: [Src::ZERO.fneg(), *src],
saturate: false,
rnd_mode: FRndMode::NearestEven,
ftz: false,
@ -261,7 +261,7 @@ pub trait LegalizeBuildHelpers: SSABuilder {
let val = self.alloc_ssa_vec(reg_file, 2);
self.push_op(OpDAdd {
dst: val.into(),
srcs: [Src::new_zero().fneg(), *src],
srcs: [Src::ZERO.fneg(), *src],
rnd_mode: FRndMode::NearestEven,
});
*src = val.into();
@ -280,7 +280,7 @@ pub trait LegalizeBuildHelpers: SSABuilder {
let val = self.alloc_ssa(reg_file);
if self.sm() >= 70 {
self.push_op(OpIAdd3 {
srcs: [Src::new_zero(), *src, Src::new_zero()],
srcs: [Src::ZERO, *src, Src::ZERO],
overflow: [Dst::None, Dst::None],
dst: val.into(),
});
@ -288,7 +288,7 @@ pub trait LegalizeBuildHelpers: SSABuilder {
self.push_op(OpIAdd2 {
dst: val.into(),
carry_out: Dst::None,
srcs: [Src::new_zero(), *src],
srcs: [Src::ZERO, *src],
});
}
*src = val.into();

4
src/nouveau/compiler/nak/lower_copy_swap.rs
View file

@ -84,7 +84,7 @@ impl LowerCopySwap {
self.slm_size = max(self.slm_size, addr + 4);
b.push_op(OpLd {
dst: copy.dst,
addr: Src::new_zero(),
addr: Src::ZERO,
offset: addr.try_into().unwrap(),
access: access,
});
@ -162,7 +162,7 @@ impl LowerCopySwap {
let addr = self.slm_start + dst_reg.base_idx() * 4;
self.slm_size = max(self.slm_size, addr + 4);
b.push_op(OpSt {
addr: Src::new_zero(),
addr: Src::ZERO,
data: copy.src,
offset: addr.try_into().unwrap(),
access: access,

2
src/nouveau/compiler/nak/opt_copy_prop.rs
View file

@ -117,7 +117,7 @@ impl CopyPropPass {
assert!(dst.comps() == 2);
match src.src_ref {
SrcRef::Zero | SrcRef::Imm32(_) => {
self.add_copy(bi, dst[0], SrcType::ALU, Src::new_zero());
self.add_copy(bi, dst[0], SrcType::ALU, Src::ZERO);
self.add_copy(bi, dst[1], SrcType::F64, src);
}
SrcRef::CBuf(cb) => {

12
src/nouveau/compiler/nak/sm70_encode.rs
View file

@ -674,7 +674,7 @@ impl SM70Op for OpFAdd {
0x021,
Some(&self.dst),
Some(&self.srcs[0]),
Some(&Src::new_zero()),
Some(&Src::ZERO),
Some(&self.srcs[1]),
)
};
@ -722,7 +722,7 @@ impl SM70Op for OpFMnMx {
Some(&self.dst),
Some(&self.srcs[0]),
Some(&self.srcs[1]),
Some(&Src::new_zero()),
Some(&Src::ZERO),
);
e.set_pred_src(87..90, 90, self.min);
e.set_bit(80, self.ftz);
@ -743,7 +743,7 @@ impl SM70Op for OpFMul {
Some(&self.dst),
Some(&self.srcs[0]),
Some(&self.srcs[1]),
Some(&Src::new_zero()),
Some(&Src::ZERO),
);
e.set_bit(76, self.dnz);
e.set_bit(77, self.saturate);
@ -1360,7 +1360,7 @@ impl SM70Op for OpIAdd3X {
if !src0.src_mod.is_none() && !src1.src_mod.is_none() {
let val = b.alloc_ssa(gpr);
b.push_op(OpIAdd3X {
srcs: [Src::new_zero(), *src0, Src::new_zero()],
srcs: [Src::ZERO, *src0, Src::ZERO],
overflow: [Dst::None, Dst::None],
dst: val.into(),
carry: [false.into(); 2],
@ -1900,7 +1900,7 @@ impl SM70Op for OpF2FP {
Some(&self.dst),
Some(&self.srcs[0]),
Some(&self.srcs[1]),
Some(&Src::new_zero()),
Some(&Src::ZERO),
);
// .MERGE_C behavior
@ -3549,7 +3549,7 @@ impl SM70Op for OpOutFinal {
0x124,
Some(&Dst::None),
Some(&self.handle),
Some(&Src::new_zero()),
Some(&Src::ZERO),
None,
);
}

10
src/nouveau/compiler/nak/spill_values.rs
View file

@ -142,11 +142,7 @@ impl Spill for SpillPred<'_> {
assert!(matches!(dst.file(), RegFile::GPR | RegFile::UGPR));
self.info.num_spills_to_reg += 1;
if let Some(b) = src.as_bool() {
let u32_src = if b {
Src::new_imm_u32(!0)
} else {
Src::new_zero()
};
let u32_src = Src::from(if b { !0 } else { 0 });
Instr::new_boxed(OpCopy {
dst: dst.into(),
src: u32_src,
@ -155,7 +151,7 @@ impl Spill for SpillPred<'_> {
Instr::new_boxed(OpSel {
dst: dst.into(),
cond: src.bnot(),
srcs: [Src::new_zero(), Src::new_imm_u32(!0)],
srcs: [0.into(), (!0).into()],
})
}
}
@ -169,7 +165,7 @@ impl Spill for SpillPred<'_> {
cmp_op: IntCmpOp::Ne,
cmp_type: IntCmpType::U32,
ex: false,
srcs: [Src::new_zero(), src.into()],
srcs: [0.into(), src.into()],
accum: true.into(),
low_cmp: true.into(),
})