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i965/hsw: Change L3 MOCS for depth, hiz, and stencil

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Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
This commit is contained in:
Chad Versace 2013-07-18 10:07:30 -07:00
parent 2273b652bb
commit 30f33deccb
2 changed files with 9 additions and 4 deletions
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6
src/mesa/drivers/dri/i965/gen7_blorp.cpp
View file

@ -662,6 +662,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t draw_x = params->depth.x_offset;
uint32_t draw_y = params->depth.y_offset;
uint32_t tile_mask_x, tile_mask_y;
uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
brw_get_depthstencil_tile_masks(params->depth.mt,
params->depth.level,
@ -713,7 +714,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
offset);
OUT_BATCH((params->depth.width + tile_x - 1) << 4 |
(params->depth.height + tile_y - 1) << 18);
OUT_BATCH(0);
OUT_BATCH(mocs);
OUT_BATCH(tile_x |
tile_y << 16);
OUT_BATCH(0);
@ -730,7 +731,8 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(hiz_region->pitch - 1);
OUT_BATCH((mocs << 25) |
(hiz_region->pitch - 1));
OUT_RELOC(hiz_region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
hiz_offset);

7
src/mesa/drivers/dri/i965/gen7_misc_state.c
View file

@ -40,6 +40,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t tile_x, uint32_t tile_y)
{
struct gl_context *ctx = &brw->ctx;
uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
intel_emit_depth_stall_flushes(brw);
@ -63,7 +64,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(((width + tile_x - 1) << 4) |
((height + tile_y - 1) << 18));
OUT_BATCH(0);
OUT_BATCH(mocs);
OUT_BATCH(tile_x | (tile_y << 16));
OUT_BATCH(0);
ADVANCE_BATCH();
@ -78,7 +79,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH(hiz_mt->region->pitch - 1);
OUT_BATCH((mocs << 25) |
(hiz_mt->region->pitch - 1));
OUT_RELOC(hiz_mt->region->bo,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER,
@ -108,6 +110,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
* same text, and experiments indicate that this is necessary.
*/
OUT_BATCH(enabled |
mocs << 25 |
(2 * stencil_mt->region->pitch - 1));
OUT_RELOC(stencil_mt->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,