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aco: simplify Definition constructors

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31362>
This commit is contained in:
Daniel Schürmann 2024-09-11 11:56:38 +02:00 • committed by Marge Bot
parent b339c525f4
commit 30e7644e5f
5 changed files with 7 additions and 11 deletions
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2
src/amd/compiler/aco_builder_h.py
View file

@ -309,7 +309,7 @@ public:
}
Definition def(RegClass rc, PhysReg reg) {
return Definition(program->allocateId(rc), reg, rc);
return Definition(tmp(rc), reg);
}
inline aco_opcode w64or32(WaveSpecificOpcode opcode) const {

2
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -11434,7 +11434,7 @@ add_startpgm(struct isel_context* ctx)
Temp elems[16];
for (unsigned j = 0; j < size; j++) {
elems[j] = ctx->program->allocateTmp(s1);
startpgm->definitions[arg++] = Definition(elems[j].id(), PhysReg{reg + j}, s1);
startpgm->definitions[arg++] = Definition(elems[j], PhysReg{reg + j});
}
ctx->arg_temps[i] = create_vec_from_array(ctx, elems, size, RegType::sgpr, 4);
} else {

8
src/amd/compiler/aco_ir.h
View file

@ -908,13 +908,9 @@ public:
: temp(Temp(0, s1)), reg_(0), isFixed_(0), isKill_(0), isPrecise_(0), isInfPreserve_(0),
isNaNPreserve_(0), isSZPreserve_(0), isNUW_(0), isNoCSE_(0)
{}
Definition(uint32_t index, RegClass type) noexcept : temp(index, type) {}
explicit Definition(Temp tmp) noexcept : temp(tmp) {}
Definition(PhysReg reg, RegClass type) noexcept : temp(Temp(0, type)) { setFixed(reg); }
Definition(uint32_t tmpId, PhysReg reg, RegClass type) noexcept : temp(Temp(tmpId, type))
{
setFixed(reg);
}
explicit Definition(PhysReg reg, RegClass type) noexcept : temp(Temp(0, type)) { setFixed(reg); }
explicit Definition(Temp tmp, PhysReg reg) noexcept : temp(tmp) { setFixed(reg); }
constexpr bool isTemp() const noexcept { return tempId() > 0; }

2
src/amd/compiler/aco_lower_to_hw_instr.cpp
View file

@ -1206,7 +1206,7 @@ split_copy(lower_context* ctx, unsigned offset, Definition* def, Operand* op,
break;
}
*def = Definition(src.def.tempId(), def_reg, src.def.regClass().resize(bytes));
*def = Definition(def_reg, src.def.regClass().resize(bytes));
if (src.op.isConstant()) {
assert(bytes >= 1 && bytes <= 8);
uint64_t val = src.op.constantValue64() >> (offset * 8u);

4
src/amd/compiler/aco_register_allocation.cpp
View file

@ -2515,7 +2515,7 @@ init_reg_file(ra_ctx& ctx, const std::vector<IDSet>& live_out_per_block, Block&
add_rename(ctx, val, renamed);
assignment& var = ctx.assignments[renamed.id()];
assert(var.assigned);
register_file.fill(Definition(renamed.id(), var.reg, var.rc));
register_file.fill(Definition(renamed, var.reg));
}
} else {
/* rename phi operands */
@ -2539,7 +2539,7 @@ init_reg_file(ra_ctx& ctx, const std::vector<IDSet>& live_out_per_block, Block&
assignment& var = ctx.assignments[renamed.id()];
/* due to live-range splits, the live-in might be a phi, now */
if (var.assigned) {
register_file.fill(Definition(renamed.id(), var.reg, var.rc));
register_file.fill(Definition(renamed, var.reg));
}
if (renamed != val) {
add_rename(ctx, val, renamed);