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radeonsi: fix maximum advertised point size / line width

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The hardware registers store the half-size/width in 12.4 fixed point
format, so 8192 is the maximum.

Fixes dEQP-GLES3.functional.rasterization.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle 2017-09-17 11:59:37 +02:00
parent a3fa3b2e02
commit 30e37289ea
2 changed files with 3 additions and 8 deletions
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7
src/gallium/drivers/radeon/r600_pipe_common.c
View file

@ -1004,17 +1004,12 @@ static const char* r600_get_name(struct pipe_screen* pscreen)
static float r600_get_paramf(struct pipe_screen* pscreen,
enum pipe_capf param)
{
struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
switch (param) {
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
case PIPE_CAPF_MAX_POINT_WIDTH:
case PIPE_CAPF_MAX_POINT_WIDTH_AA:
if (rscreen->family >= CHIP_CEDAR)
return 16384.0f;
else
return 8192.0f;
return 8192.0f;
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:

4
src/gallium/drivers/radeonsi/si_state.c
View file

@ -902,8 +902,8 @@ static void *si_create_rs_state(struct pipe_context *ctx,
S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
tmp = (unsigned)state->line_width * 8;
si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
S_028A48_MSAA_ENABLE(state->multisample ||