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nir: add nir_texop_descriptor_amd

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AMD will use it to emulate resinfo.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17693>
This commit is contained in:
Marek Olšák 2022-07-20 22:55:04 -04:00 • committed by Marge Bot
parent 6483fd394e
commit 3098000e71
3 changed files with 11 additions and 0 deletions
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5
src/compiler/nir/nir.c
View file

@ -3215,6 +3215,7 @@ nir_tex_instr_need_sampler(const nir_tex_instr *instr)
case nir_texop_query_levels:
case nir_texop_texture_samples:
case nir_texop_samples_identical:
case nir_texop_descriptor_amd:
return false;
default:
return true;
@ -3260,6 +3261,9 @@ nir_tex_instr_result_size(const nir_tex_instr *instr)
case nir_texop_fragment_mask_fetch_amd:
return 1;
case nir_texop_descriptor_amd:
return instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? 4 : 8;
default:
if (instr->is_shadow && instr->is_new_style_shadow)
return 1;
@ -3276,6 +3280,7 @@ nir_tex_instr_is_query(const nir_tex_instr *instr)
case nir_texop_lod:
case nir_texop_texture_samples:
case nir_texop_query_levels:
case nir_texop_descriptor_amd:
return true;
case nir_texop_tex:
case nir_texop_txb:

1
src/compiler/nir/nir.h
View file

@ -2154,6 +2154,7 @@ typedef enum {
nir_texop_tex_prefetch, /**< Regular texture look-up, eligible for pre-dispatch */
nir_texop_fragment_fetch_amd, /**< Multisample fragment color texture fetch */
nir_texop_fragment_mask_fetch_amd, /**< Multisample fragment mask texture fetch */
nir_texop_descriptor_amd, /**< Returns a buffer or image descriptor. */
} nir_texop;
/** Represents a texture instruction */

5
src/compiler/spirv/spirv_to_nir.c
View file

@ -2826,8 +2826,13 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp opcode,
break;
case nir_texop_txf_ms_mcs_intel:
vtn_fail("unexpected nir_texop_txf_ms_mcs");
break;
case nir_texop_tex_prefetch:
vtn_fail("unexpected nir_texop_tex_prefetch");
break;
case nir_texop_descriptor_amd:
vtn_fail("unexpected nir_texop_descriptor_amd");
break;
}
unsigned idx = 4;