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radeonsi: Add compute support v3
v2: - Only dump shaders when env variable is set. v3: - Don't emit VGT registers Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com
This commit is contained in:
Tom Stellard
parent
4f7fe2cf2c
commit
302f53dc20
11 changed files with 378 additions and 49 deletions
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@ -30,7 +30,7 @@
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#include <llvm-c/BitReader.h>
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#include <llvm-c/Core.h>
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static LLVMModuleRef radeon_llvm_parse_bitcode(const unsigned char * bitcode,
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LLVMModuleRef radeon_llvm_parse_bitcode(const unsigned char * bitcode,
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unsigned bitcode_len)
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{
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LLVMMemoryBufferRef buf;
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@ -29,6 +29,8 @@
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#include <llvm-c/Core.h>
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LLVMModuleRef radeon_llvm_parse_bitcode(const unsigned char * bitcode,
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unsigned bitcode_len);
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unsigned radeon_llvm_get_num_kernels(const unsigned char *bitcode, unsigned bitcode_len);
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LLVMModuleRef radeon_llvm_get_kernel_module(unsigned index,
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const unsigned char *bitcode, unsigned bitcode_len);
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@ -9,6 +9,7 @@ C_SOURCES := \
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r600_texture.c \
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r600_translate.c \
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radeonsi_pm4.c \
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radeonsi_compute.c \
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si_state.c \
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si_state_streamout.c \
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si_state_draw.c \
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234
src/gallium/drivers/radeonsi/radeonsi_compute.c
Normal file
234
src/gallium/drivers/radeonsi/radeonsi_compute.c
Normal file
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@ -0,0 +1,234 @@
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#include "util/u_memory.h"
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#include "radeonsi_pipe.h"
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#include "radeonsi_shader.h"
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#include "radeon_llvm_util.h"
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struct si_pipe_compute {
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struct r600_context *ctx;
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unsigned local_size;
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unsigned private_size;
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unsigned input_size;
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struct si_pipe_shader shader;
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unsigned num_user_sgprs;
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struct si_pm4_state *pm4_buffers;
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};
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static void *radeonsi_create_compute_state(
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struct pipe_context *ctx,
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const struct pipe_compute_state *cso)
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{
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struct r600_context *rctx = (struct r600_context *)ctx;
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struct si_pipe_compute *program =
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CALLOC_STRUCT(si_pipe_compute);
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const struct pipe_llvm_program_header *header;
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const unsigned char *code;
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LLVMModuleRef mod;
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header = cso->prog;
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code = cso->prog + sizeof(struct pipe_llvm_program_header);
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program->ctx = rctx;
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program->local_size = cso->req_local_mem;
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program->private_size = cso->req_private_mem;
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program->input_size = cso->req_input_mem;
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mod = radeon_llvm_parse_bitcode(code, header->num_bytes);
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si_compile_llvm(rctx, &program->shader, mod);
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return program;
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}
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static void radeonsi_bind_compute_state(struct pipe_context *ctx, void *state)
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{
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struct r600_context *rctx = (struct r600_context*)ctx;
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rctx->cs_shader_state.program = (struct si_pipe_compute*)state;
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}
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static void radeonsi_set_global_binding(
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struct pipe_context *ctx, unsigned first, unsigned n,
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struct pipe_resource **resources,
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uint32_t **handles)
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{
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unsigned i;
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struct r600_context *rctx = (struct r600_context*)ctx;
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struct si_pipe_compute *program = rctx->cs_shader_state.program;
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struct si_pm4_state *pm4;
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if (!program->pm4_buffers) {
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program->pm4_buffers = CALLOC_STRUCT(si_pm4_state);
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}
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pm4 = program->pm4_buffers;
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pm4->compute_pkt = true;
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if (!resources) {
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return;
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}
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for (i = first; i < first + n; i++) {
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uint64_t va = r600_resource_va(ctx->screen, resources[i]);
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si_pm4_add_bo(pm4, (struct si_resource*)resources[i],
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RADEON_USAGE_READWRITE);
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memcpy(handles[i], &va, sizeof(va));
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}
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}
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static void radeonsi_launch_grid(
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struct pipe_context *ctx,
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const uint *block_layout, const uint *grid_layout,
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uint32_t pc, const void *input)
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{
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struct r600_context *rctx = (struct r600_context*)ctx;
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struct si_pipe_compute *program = rctx->cs_shader_state.program;
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struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
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uint64_t shader_va;
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unsigned arg_user_sgpr_count;
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unsigned i;
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pm4->compute_pkt = true;
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si_cmd_context_control(pm4);
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si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
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si_pm4_cmd_add(pm4, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) |
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EVENT_INDEX(0x7) |
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EVENT_WRITE_INV_L2);
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si_pm4_cmd_end(pm4, false);
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si_pm4_inval_texture_cache(pm4);
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si_pm4_inval_shader_cache(pm4);
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si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
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arg_user_sgpr_count = program->input_size / 4;
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if (program->input_size % 4 != 0) {
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arg_user_sgpr_count++;
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}
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/* XXX: We should store arguments in memory if we run out of user sgprs.
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*/
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assert(arg_user_sgpr_count < 16);
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for (i = 0; i < arg_user_sgpr_count; i++) {
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uint32_t *args = (uint32_t*)input;
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si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 +
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(i * 4),
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args[i]);
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}
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si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
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si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
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si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
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si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
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S_00B81C_NUM_THREAD_FULL(block_layout[0]));
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si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
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S_00B820_NUM_THREAD_FULL(block_layout[1]));
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si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
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S_00B824_NUM_THREAD_FULL(block_layout[2]));
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/* XXX: This should be:
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* (number of compute units) * 4 * (waves per simd) - 1 */
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si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
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shader_va = r600_resource_va(ctx->screen, (void *)program->shader.bo);
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si_pm4_add_bo(pm4, program->shader.bo, RADEON_USAGE_READ);
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si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
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si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
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si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
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/* We always use at least 3 VGPRS, these come from
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* TIDIG_COMP_CNT.
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* XXX: The compiler should account for this.
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*/
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S_00B848_VGPRS((MAX2(3, program->shader.num_vgprs) - 1) / 4)
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/* We always use at least 4 + arg_user_sgpr_count. The 4 extra
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* sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
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* XXX: The compiler should account for this.
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*/
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| S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
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program->shader.num_sgprs)) - 1) / 8))
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;
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si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
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S_00B84C_SCRATCH_EN(0)
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| S_00B84C_USER_SGPR(arg_user_sgpr_count)
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| S_00B84C_TGID_X_EN(1)
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| S_00B84C_TGID_Y_EN(1)
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| S_00B84C_TGID_Z_EN(1)
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| S_00B84C_TG_SIZE_EN(1)
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| S_00B84C_TIDIG_COMP_CNT(2)
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| S_00B84C_LDS_SIZE(0)
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| S_00B84C_EXCP_EN(0))
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;
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si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
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si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
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S_00B858_SH0_CU_EN(0xffff /* Default value */)
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| S_00B858_SH1_CU_EN(0xffff /* Default value */))
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;
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si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
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S_00B85C_SH0_CU_EN(0xffff /* Default value */)
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| S_00B85C_SH1_CU_EN(0xffff /* Default value */))
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;
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si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
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si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
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si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
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si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
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si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
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si_pm4_cmd_end(pm4, false);
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si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
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si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
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si_pm4_cmd_end(pm4, false);
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si_pm4_inval_texture_cache(pm4);
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si_pm4_inval_shader_cache(pm4);
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si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
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si_pm4_emit(rctx, program->pm4_buffers);
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si_pm4_emit(rctx, pm4);
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#if 0
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fprintf(stderr, "cdw: %i\n", rctx->cs->cdw);
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for (i = 0; i < rctx->cs->cdw; i++) {
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fprintf(stderr, "%4i : 0x%08X\n", i, rctx->cs->buf[i]);
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}
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#endif
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rctx->ws->cs_flush(rctx->cs, RADEON_FLUSH_COMPUTE);
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rctx->ws->buffer_wait(program->shader.bo->buf, 0);
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FREE(pm4);
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}
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static void si_delete_compute_state(struct pipe_context *ctx, void* state){}
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static void si_set_compute_resources(struct pipe_context * ctx_,
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unsigned start, unsigned count,
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struct pipe_surface ** surfaces) { }
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static void si_set_cs_sampler_view(struct pipe_context *ctx_,
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unsigned start_slot, unsigned count,
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struct pipe_sampler_view **views) { }
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static void si_bind_compute_sampler_states(
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struct pipe_context *ctx_,
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unsigned start_slot,
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unsigned num_samplers,
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void **samplers_) { }
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void si_init_compute_functions(struct r600_context *rctx)
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{
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rctx->context.create_compute_state = radeonsi_create_compute_state;
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rctx->context.delete_compute_state = si_delete_compute_state;
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rctx->context.bind_compute_state = radeonsi_bind_compute_state;
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/* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
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rctx->context.set_compute_resources = si_set_compute_resources;
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rctx->context.set_compute_sampler_views = si_set_cs_sampler_view;
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rctx->context.bind_compute_sampler_states = si_bind_compute_sampler_states;
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rctx->context.set_global_binding = radeonsi_set_global_binding;
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rctx->context.launch_grid = radeonsi_launch_grid;
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}
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@ -217,6 +217,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
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r600_init_query_functions(rctx);
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r600_init_context_resource_functions(rctx);
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si_init_surface_functions(rctx);
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si_init_compute_functions(rctx);
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rctx->context.create_video_decoder = vl_create_decoder;
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rctx->context.create_video_buffer = vl_video_buffer_create;
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@ -342,6 +343,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
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case PIPE_CAP_TGSI_INSTANCEID:
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case PIPE_CAP_COMPUTE:
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return 1;
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case PIPE_CAP_TGSI_TEXCOORD:
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return 0;
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@ -366,7 +368,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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case PIPE_CAP_USER_VERTEX_BUFFERS:
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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case PIPE_CAP_COMPUTE:
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case PIPE_CAP_QUERY_TIMESTAMP:
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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case PIPE_CAP_CUBE_MAP_ARRAY:
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@ -450,6 +451,13 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
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case PIPE_SHADER_GEOMETRY:
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/* TODO: support and enable geometry programs */
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return 0;
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case PIPE_SHADER_COMPUTE:
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switch (param) {
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case PIPE_SHADER_CAP_PREFERRED_IR:
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return PIPE_SHADER_IR_LLVM;
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default:
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return 0;
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}
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default:
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/* TODO: support tessellation */
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return 0;
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@ -516,6 +524,56 @@ static int r600_get_video_param(struct pipe_screen *screen,
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}
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}
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static int r600_get_compute_param(struct pipe_screen *screen,
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enum pipe_compute_cap param,
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void *ret)
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{
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struct r600_screen *rscreen = (struct r600_screen *)screen;
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//TODO: select these params by asic
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switch (param) {
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case PIPE_COMPUTE_CAP_IR_TARGET: {
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const char *gpu = r600_get_llvm_processor_name(rscreen->family);
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if (ret) {
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sprintf(ret, "%s-r600--", gpu);
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}
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return (8 + strlen(gpu)) * sizeof(char);
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}
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case PIPE_COMPUTE_CAP_GRID_DIMENSION:
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if (ret) {
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uint64_t * grid_dimension = ret;
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grid_dimension[0] = 3;
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}
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return 1 * sizeof(uint64_t);
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case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
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if (ret) {
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uint64_t * grid_size = ret;
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grid_size[0] = 65535;
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grid_size[1] = 65535;
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grid_size[2] = 1;
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}
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return 3 * sizeof(uint64_t) ;
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case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
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if (ret) {
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uint64_t * block_size = ret;
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block_size[0] = 256;
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block_size[1] = 256;
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block_size[2] = 256;
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}
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return 3 * sizeof(uint64_t);
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case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
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if (ret) {
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uint64_t * max_threads_per_block = ret;
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*max_threads_per_block = 256;
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}
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return sizeof(uint64_t);
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default:
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fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
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return 0;
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}
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}
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static void r600_destroy_screen(struct pipe_screen* pscreen)
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{
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struct r600_screen *rscreen = (struct r600_screen *)pscreen;
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@ -727,6 +785,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
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rscreen->screen.get_shader_param = r600_get_shader_param;
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rscreen->screen.get_paramf = r600_get_paramf;
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rscreen->screen.get_video_param = r600_get_video_param;
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rscreen->screen.get_compute_param = r600_get_compute_param;
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rscreen->screen.is_format_supported = si_is_format_supported;
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rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
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rscreen->screen.context_create = r600_create_context;
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@ -50,6 +50,8 @@
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#define R600_TRACE_CS 0
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#define R600_TRACE_CS_DWORDS 6
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struct si_pipe_compute;
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struct r600_pipe_fences {
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struct si_resource *bo;
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unsigned *data;
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@ -88,6 +90,10 @@ struct si_pipe_sampler_state {
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float border_color[4];
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};
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struct si_cs_shader_state {
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struct si_pipe_compute *program;
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};
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/* needed for blitter save */
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#define NUM_TEX_UNITS 16
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@ -139,6 +145,7 @@ struct r600_context {
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struct pipe_stencil_ref stencil_ref;
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struct si_pipe_shader_selector *ps_shader;
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struct si_pipe_shader_selector *vs_shader;
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struct si_cs_shader_state cs_shader_state;
|
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struct pipe_query *current_render_cond;
|
||||
unsigned current_render_cond_mode;
|
||||
struct pipe_query *saved_render_cond;
|
||||
|
|
@ -239,6 +246,9 @@ void r600_translate_index_buffer(struct r600_context *r600,
|
|||
void r600_trace_emit(struct r600_context *rctx);
|
||||
#endif
|
||||
|
||||
/* radeonsi_compute.c */
|
||||
void si_init_compute_functions(struct r600_context *rctx);
|
||||
|
||||
/*
|
||||
* common helpers
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -47,8 +47,9 @@ void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
|
|||
{
|
||||
unsigned count;
|
||||
count = state->ndw - state->last_pm4 - 2;
|
||||
state->pm4[state->last_pm4] = PKT3(state->last_opcode,
|
||||
count, predicate);
|
||||
state->pm4[state->last_pm4] =
|
||||
PKT3(state->last_opcode, count, predicate)
|
||||
| PKT3_SHADER_TYPE_S(state->compute_pkt);
|
||||
|
||||
assert(state->ndw <= SI_PM4_MAX_DW);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -58,6 +58,8 @@ struct si_pm4_state
|
|||
/* relocs for shader data */
|
||||
unsigned nrelocs;
|
||||
unsigned relocs[SI_PM4_MAX_RELOCS];
|
||||
|
||||
bool compute_pkt;
|
||||
};
|
||||
|
||||
void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
|
||||
|
|
|
|||
|
|
@ -1093,6 +1093,57 @@ static void preload_samplers(struct si_shader_context *si_shader_ctx)
|
|||
}
|
||||
}
|
||||
|
||||
int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader,
|
||||
LLVMModuleRef mod)
|
||||
{
|
||||
unsigned char *inst_bytes;
|
||||
unsigned inst_byte_count;
|
||||
unsigned i;
|
||||
uint32_t *ptr;
|
||||
bool dump;
|
||||
|
||||
dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
|
||||
|
||||
radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count,
|
||||
r600_get_llvm_processor_name(rctx->screen->family),
|
||||
dump);
|
||||
|
||||
if (dump) {
|
||||
fprintf(stderr, "SI CODE:\n");
|
||||
for (i = 0; i < inst_byte_count; i+=4 ) {
|
||||
fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3],
|
||||
inst_bytes[i + 2], inst_bytes[i + 1],
|
||||
inst_bytes[i]);
|
||||
}
|
||||
}
|
||||
|
||||
shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes);
|
||||
shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4));
|
||||
shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8));
|
||||
|
||||
/* copy new shader */
|
||||
si_resource_reference(&shader->bo, NULL);
|
||||
shader->bo = si_resource_create_custom(rctx->context.screen, PIPE_USAGE_IMMUTABLE,
|
||||
inst_byte_count - 12);
|
||||
if (shader->bo == NULL) {
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
|
||||
if (0 /*R600_BIG_ENDIAN*/) {
|
||||
for (i = 0; i < (inst_byte_count-12)/4; ++i) {
|
||||
ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4));
|
||||
}
|
||||
} else {
|
||||
memcpy(ptr, inst_bytes + 12, inst_byte_count - 12);
|
||||
}
|
||||
rctx->ws->buffer_unmap(shader->bo->cs_buf);
|
||||
|
||||
free(inst_bytes);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int si_pipe_shader_create(
|
||||
struct pipe_context *ctx,
|
||||
struct si_pipe_shader *shader)
|
||||
|
|
@ -1103,11 +1154,8 @@ int si_pipe_shader_create(
|
|||
struct tgsi_shader_info shader_info;
|
||||
struct lp_build_tgsi_context * bld_base;
|
||||
LLVMModuleRef mod;
|
||||
unsigned char * inst_bytes;
|
||||
unsigned inst_byte_count;
|
||||
unsigned i;
|
||||
uint32_t *ptr;
|
||||
bool dump;
|
||||
int r = 0;
|
||||
|
||||
dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
|
||||
|
||||
|
|
@ -1162,55 +1210,16 @@ int si_pipe_shader_create(
|
|||
radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
|
||||
|
||||
mod = bld_base->base.gallivm->module;
|
||||
if (dump) {
|
||||
LLVMDumpModule(mod);
|
||||
}
|
||||
radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count,
|
||||
r600_get_llvm_processor_name(rctx->screen->family)
|
||||
, dump);
|
||||
if (dump) {
|
||||
fprintf(stderr, "SI CODE:\n");
|
||||
for (i = 0; i < inst_byte_count; i+=4 ) {
|
||||
fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3],
|
||||
inst_bytes[i + 2], inst_bytes[i + 1],
|
||||
inst_bytes[i]);
|
||||
}
|
||||
}
|
||||
|
||||
shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes);
|
||||
shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4));
|
||||
shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8));
|
||||
r = si_compile_llvm(rctx, shader, mod);
|
||||
|
||||
radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
|
||||
tgsi_parse_free(&si_shader_ctx.parse);
|
||||
|
||||
/* copy new shader */
|
||||
si_resource_reference(&shader->bo, NULL);
|
||||
shader->bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
|
||||
inst_byte_count - 12);
|
||||
if (shader->bo == NULL) {
|
||||
FREE(si_shader_ctx.constants);
|
||||
FREE(si_shader_ctx.resources);
|
||||
FREE(si_shader_ctx.samplers);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
|
||||
if (0 /*R600_BIG_ENDIAN*/) {
|
||||
for (i = 0; i < (inst_byte_count-12)/4; ++i) {
|
||||
ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4));
|
||||
}
|
||||
} else {
|
||||
memcpy(ptr, inst_bytes + 12, inst_byte_count - 12);
|
||||
}
|
||||
rctx->ws->buffer_unmap(shader->bo->cs_buf);
|
||||
|
||||
FREE(si_shader_ctx.constants);
|
||||
FREE(si_shader_ctx.resources);
|
||||
FREE(si_shader_ctx.samplers);
|
||||
free(inst_bytes);
|
||||
|
||||
return 0;
|
||||
return r;
|
||||
}
|
||||
|
||||
void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
#ifndef RADEONSI_SHADER_H
|
||||
#define RADEONSI_SHADER_H
|
||||
|
||||
#include <llvm-c/Core.h> /* LLVMModuleRef */
|
||||
|
||||
#define SI_SGPR_CONST 0
|
||||
#define SI_SGPR_SAMPLER 2
|
||||
#define SI_SGPR_RESOURCE 4
|
||||
|
|
@ -142,6 +144,9 @@ struct si_pipe_shader {
|
|||
|
||||
/* radeonsi_shader.c */
|
||||
int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
|
||||
int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
|
||||
int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader,
|
||||
LLVMModuleRef mod);
|
||||
void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#define SI_CONTEXT_REG_OFFSET 0x00028000
|
||||
#define SI_CONTEXT_REG_END 0x00029000
|
||||
|
||||
#define EVENT_TYPE_CACHE_FLUSH 0x6
|
||||
#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
|
||||
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
|
||||
#define EVENT_TYPE_ZPASS_DONE 0x15
|
||||
|
|
@ -47,6 +48,8 @@
|
|||
* 4 - *S_PARTIAL_FLUSH
|
||||
* 5 - TS events
|
||||
*/
|
||||
#define EVENT_WRITE_INV_L2 0x100000
|
||||
|
||||
|
||||
#define PREDICATION_OP_CLEAR 0x0
|
||||
#define PREDICATION_OP_ZPASS 0x1
|
||||
|
|
@ -65,6 +68,8 @@
|
|||
#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7
|
||||
|
||||
#define PKT3_NOP 0x10
|
||||
#define PKT3_DISPATCH_DIRECT 0x15
|
||||
#define PKT3_DISPATCH_INDIRECT 0x16
|
||||
#define PKT3_SET_PREDICATION 0x20
|
||||
#define PKT3_COND_EXEC 0x22
|
||||
#define PKT3_PRED_EXEC 0x23
|
||||
|
|
@ -122,6 +127,7 @@
|
|||
#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF)
|
||||
#define PKT3_IT_OPCODE_C 0xFFFF00FF
|
||||
#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
|
||||
#define PKT3_SHADER_TYPE_S(x) (((x) & 0x1) << 1)
|
||||
#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
|
||||
#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate))
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue