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radv: enable DCC for MSAA 2x textures on VI under an option

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This can be enabled with RADV_PERFTEST=dccmsaa.

DCC for MSAA textures is actually not as easy to implement. It
looks like there is some corner cases. I will improve support
incrementally.

Vega support, as well as Polaris improvements, will be added later.

No CTS changes on Polaris using RADV_DEBUG=zerovram and
RADV_PERFTEST=dccmsaa.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2018-04-17 16:05:18 +02:00
parent dc3d39771f
commit 2f63b3dd09
4 changed files with 13 additions and 1 deletions
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1
src/amd/vulkan/radv_debug.h
View file

@ -51,6 +51,7 @@ enum {
RADV_PERFTEST_LOCAL_BOS = 0x4, RADV_PERFTEST_LOCAL_BOS = 0x4,
RADV_PERFTEST_BINNING = 0x8, RADV_PERFTEST_BINNING = 0x8,
RADV_PERFTEST_OUT_OF_ORDER = 0x10, RADV_PERFTEST_OUT_OF_ORDER = 0x10,
RADV_PERFTEST_DCC_MSAA = 0x20,
}; };
bool bool

4
src/amd/vulkan/radv_device.c
View file

@ -314,6 +314,9 @@ radv_physical_device_init(struct radv_physical_device *device,
device->out_of_order_rast_allowed = device->has_out_of_order_rast && device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
(device->instance->perftest_flags & RADV_PERFTEST_OUT_OF_ORDER); (device->instance->perftest_flags & RADV_PERFTEST_OUT_OF_ORDER);
device->dcc_msaa_allowed = device->rad_info.chip_class == VI &&
(device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
radv_physical_device_init_mem_types(device); radv_physical_device_init_mem_types(device);
radv_fill_device_extension_table(device, &device->supported_extensions); radv_fill_device_extension_table(device, &device->supported_extensions);
@ -399,6 +402,7 @@ static const struct debug_control radv_perftest_options[] = {
{"localbos", RADV_PERFTEST_LOCAL_BOS}, {"localbos", RADV_PERFTEST_LOCAL_BOS},
{"binning", RADV_PERFTEST_BINNING}, {"binning", RADV_PERFTEST_BINNING},
{"outoforderrast", RADV_PERFTEST_OUT_OF_ORDER}, {"outoforderrast", RADV_PERFTEST_OUT_OF_ORDER},
{"dccmsaa", RADV_PERFTEST_DCC_MSAA},
{NULL, 0} {NULL, 0}
}; };

6
src/amd/vulkan/radv_image.c
View file

@ -133,8 +133,12 @@ radv_use_dcc_for_image(struct radv_device *device,
if (create_info->scanout) if (create_info->scanout)
return false; return false;
/* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet. */
if (pCreateInfo->samples > 2)
return false;
/* TODO: Enable DCC for MSAA textures. */ /* TODO: Enable DCC for MSAA textures. */
if (pCreateInfo->samples >= 2) if (!device->physical_device->dcc_msaa_allowed)
return false; return false;
/* Determine if the formats are DCC compatible. */ /* Determine if the formats are DCC compatible. */

3
src/amd/vulkan/radv_private.h
View file

@ -295,6 +295,9 @@ struct radv_physical_device {
bool has_out_of_order_rast; bool has_out_of_order_rast;
bool out_of_order_rast_allowed; bool out_of_order_rast_allowed;
/* Whether DCC should be enabled for MSAA textures. */
bool dcc_msaa_allowed;
/* This is the drivers on-disk cache used as a fallback as opposed to /* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps. * the pipeline cache defined by apps.
*/ */